Open defects have been intentionally designed in a set of interconnect metal lines. In order to improve the controllability and the observability of the experimental design, a simple bus structure with a scan register followed by a hold register is used to manage the set of interconnect lines. The strength of the open defects has been varied within a realistic range of resistances ranging from a full (complete) open to a weak (low resistance) open by means of broken metal lines and transmission gates, respectively. Experiments performed with an automatic test equipment show the influence of coupling capacitances with adjacent lines on the electrical behavior of the defective line. Furthermore, experimental evidence of the history effect on the delay caused by resistive opens is investigated. Validation of the measured results by means of theoretical as well as simulation analysis is presented. Finally, some recommendations to generate stuck-at, I_DDQ and delay test are discussed in order to improve the detectability of such defects.

Defective interconnect lines affected by open defects have been intentionally designed and introduced on a CMOS digital test circuit. A simple bus structure with a scan register followed by a hold register and two buffers is used to investigate the influence of the crosstalk capacitances of the adjacent lines to the open defect. The strength of the open defect has been varied within a realistic range of resistances going from a full (complete) open up to a weak (low-resistive) open. The static and dynamic behavior of the defective lines have been electrically characterized taking into account the location of the defect as well as its resistive value. This characterization allows the extraction of general information useful for the prediction and detection of the faulty behavior caused by the defect. Testability conditions of this defect in interconnect lines are discussed.

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.

Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One of the most powerful techniques to compromise the correct functioning of a device are fault injection attacks. They enable an active adversary to trigger errors on a circuit in order to bypass security features or to gain knowledge of security-sensitive information. There are several methods to induce such errors. In this work we focus on the injection of faults through the electromagnetic (EM) channel. In particular, we document our efforts towards building a suitable platform for EM pulse injection. We design a pulse injection circuit that can provide currents over 20 A to an EM injector in order to generate abrupt variations of the EM field on the vicinity of a circuit. We validate the suitability of our platform by applying a well-know attack on an embedded 8-bit microcontroller implementing the AES block cipher. In particular, we show how to extract the AES secret cryptographic keys stored in the device by careful injection of faults during the encryption operations and simple analysis of the erroneous outputs.

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.