This paper proposes a neural stimulation integrated circuit design with multiple current output modes. In the cathodic stimulation phase and anodic stimulation phase, each output current waveform can be independently selected to either exponential waveform or square wave, so the stimulator holds four stimulation modes. To minimize the headroom voltage of the output stage and enhance the power efficiency of the proposed stimulator, we introduce the exponentially decaying current which is realized by the exponential current generation circuit in this work. It can enhance the longer duration of the stimulation pulse as well. In case the residual charge may cause harm to patients, a charge balancing technique is implemented in this work for all operation modes. The four-channel stimulator IC is implemented in a 180-nm CMOS process, occupying a core area of 1.93 mm ² . The measurement results show that the proposed stimulator realized a maximum power efficiency of 91.3% and the maximum stimulation duration is 3 times larger than previous works. Moreover, even in exponential output waveform mode, the maximum residual charge in a single cycle is only 255 pC due to the proposed charge balancing technique. The experiment results based on the PBS solution also show that the stimulator IC can remove residual charges within 60 μs, and the electrode voltage remains stable within a safe range under multicycle stimulation.

The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

A photonic multi-format background-free binarily modulated microwave signal generator using a single dual-polarization dual-parallel Mach–Zehnder modulator is proposed and demonstrated. The proposed generator features good reconfiguration and switchability. By simply adjusting the direct current biases of the modulator, amplitude shift keying (ASK), phase shift keying (PSK) and frequency-shift keying (FSK) microwave signals can be generated. Benefiting from the complementary intensity modulation, there is no residual baseband modulated signal in the generated binarily modulated signals. The system does not involve any optical or electrical filters, which ensures good tunability of the generator. By changing the frequency of the driven microwave carrier and bit rate of the electrical coded signal, the frequency and rate of the generated multi-format signals can be adjusted accordingly. The multi-format switchable signal generator has great potential in multi-functional communication and radar systems.

Reconstruction algorithms are an integral part of compressed sensing (CS) theory, which can reliably reconstruct the original signal from the low-dimensional compressed signal. The orthogonal matching pursuit (OMP) algorithm has been widely studied and extensively selected in hardware implementations. However, the low reconstruction success rate of the OMP algorithm under high sparsity conditions has led to the proposal and application of more reconstruction algorithms in hardware implementations. In this article, a staged projection refining multiple OMP (SPR-MOMP) algorithm is proposed based on the OMP algorithm. This algorithm improves the reconstruction accuracy by refining the support set using a staged backtracking strategy. It also employs a multiple-atom selection strategy for parallel expansion of the support set, ensuring reconstruction efficiency. The reconstruction simulation demonstrates that the SPR-MOMP algorithm achieves a higher reconstruction success rate than the OMP algorithm, with fewer iterations. A hardware architecture applying the SPR-MOMP algorithm is designed and implemented on a Virtex UltraScale+ field-programmable gate array (FPGA) with $N =1024$ , $M =256$ , and $K =36$ . The proposed architecture achieves a reconstruction signal-to-noise ratio (RSNR) of 44.27 dB, with 20-bit data width and 15-bit fractional width. The maximum clock frequency of the architecture is 200 MHz, enabling reconstruction within $276.6~\mu $ s. The proposed architecture achieves a lower dynamic power consumption of 1929 mW.

This paper presents a 1.9-ps 8× phase interpolation time-to-digital converter (PI-TDC). This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2.5-GS/s. The simulated DNL is 0.85-LSB, and INL is 0.64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL). The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step.