This paper proposes a neural stimulation integrated circuit design with multiple current output modes. In the cathodic stimulation phase and anodic stimulation phase, each output current waveform can be independently selected to either exponential waveform or square wave, so the stimulator holds four stimulation modes. To minimize the headroom voltage of the output stage and enhance the power efficiency of the proposed stimulator, we introduce the exponentially decaying current which is realized by the exponential current generation circuit in this work. It can enhance the longer duration of the stimulation pulse as well. In case the residual charge may cause harm to patients, a charge balancing technique is implemented in this work for all operation modes. The four-channel stimulator IC is implemented in a 180-nm CMOS process, occupying a core area of 1.93 mm ² . The measurement results show that the proposed stimulator realized a maximum power efficiency of 91.3% and the maximum stimulation duration is 3 times larger than previous works. Moreover, even in exponential output waveform mode, the maximum residual charge in a single cycle is only 255 pC due to the proposed charge balancing technique. The experiment results based on the PBS solution also show that the stimulator IC can remove residual charges within 60 μs, and the electrode voltage remains stable within a safe range under multicycle stimulation.

The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

Low noise ( ${i}_{\text {noise}}$ ) and high responsivity ( ${R}$ ) are significant factors for Lead sulfide (PbS) colloidal quantum dots (CQDs) photodetectors implementing high specific detectivity ( ${D}^{\ast} $ ). However, the simultaneous achievement of the above two factors is still challenging due to the complicated roles of interfaces and the difficulties in comprehensive interface modification by individual strategy. Here, we propose a well-designed PbS CQD near-infrared (NIR) photodiode with high performance by multi-interface engineering. First, the well-passivated interface of a photo-active layer is obtained by high-quality n-type CQD inks and gentle ligands cross-linked p-type CQD solid films, which leads to low defect density and thus extremely low device dark current ( $\sim $ 70 nA $\cdot $ cm $^{-{2}}$ ). Second, the construction of LiF and MoO _x carrier-selective layers in the electrode interfaces greatly increases the photogenerated charge carrier extraction efficiency due to the enhanced built-in electric field, which promotes a high ${R}$ to 0.61 $\text{A}\cdot \text{W}^{-{1}}$ at 1100 nm. Both the two modifications enable low ${i}_{\text {noise}}$ and high ${R}$ . Hence the device exhibits an ultrahigh ${D}^{\ast} $ up to $1.42\times 10^{{12}}$ Jones. The further demonstration of high-precision biological health monitoring in both visible and infrared bands by this device illustrates its huge potential in ultra-sensitive broadband optoelectronic applications.

A photonic multi-format background-free binarily modulated microwave signal generator using a single dual-polarization dual-parallel Mach–Zehnder modulator is proposed and demonstrated. The proposed generator features good reconfiguration and switchability. By simply adjusting the direct current biases of the modulator, amplitude shift keying (ASK), phase shift keying (PSK) and frequency-shift keying (FSK) microwave signals can be generated. Benefiting from the complementary intensity modulation, there is no residual baseband modulated signal in the generated binarily modulated signals. The system does not involve any optical or electrical filters, which ensures good tunability of the generator. By changing the frequency of the driven microwave carrier and bit rate of the electrical coded signal, the frequency and rate of the generated multi-format signals can be adjusted accordingly. The multi-format switchable signal generator has great potential in multi-functional communication and radar systems.

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm², while the power consumption is impressively low at 417 μW and FoMs is 168 dB.