Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as $I_{on}/I_{off}$ , $DIBL$ , and $SS$ , to highlight the advantages and disadvantages of each junctionless transistor category.

In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors’ geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS 0.35µm CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.

Silicon-based kinetic energy converters employing variable capacitors, also known as electrostatic vibration energy harvesters, hold promise as power sources for Internet of Things devices. However, for most wireless applications, such as wearable technology or environmental and structural monitoring, the ambient vibration is often at relatively low frequencies (1–100 Hz). Since the power output of electrostatic harvesters is positively correlated to the frequency of capacitance oscillation, typical electrostatic energy harvesters, designed to match the natural frequency of ambient vibrations, do not produce sufficient power output. Moreover, energy conversion is limited to a narrow range of input frequencies. To address these shortcomings, an impacted-based electrostatic energy harvester is explored experimentally. The impact refers to electrode collision and it triggers frequency upconversion, namely a secondary high-frequency free oscillation of the electrodes overlapping with primary device oscillation tuned to input vibration frequency. The main purpose of high-frequency oscillation is to enable additional energy conversion cycles since this will increase the energy output. The devices investigated were fabricated using a commercial microfabrication foundry process and were experimentally studied. These devices exhibit non-uniform cross-section electrodes and a springless mass. The non-uniform width electrodes were used to prevent pull-in following electrode collision. Springless masses from different materials and sizes, such as 0.5 mm diameter Tungsten carbide, 0.8 mm diameter Tungsten carbide, zirconium dioxide, and silicon nitride, were added in an attempt to force collisions over a range of applied frequencies that would not otherwise result in collisions. The results show that the system operates over a relatively wide frequency range (up to 700 Hz frequency range), with the lower limit far below the natural frequency of the device. The addition of the springless mass successfully increased the device bandwidth. For example, at a low peak-to-peak vibration acceleration of 0.5 g (peak-to-peak), the addition of a zirconium dioxide ball doubled the device’s bandwidth. Testing with different balls indicates that the different sizes and material properties have different effects on the device’s performance, altering its mechanical and electrical damping.

This article reports two low power wake-up receiver (WuRx) circuits (Type A and B) for underwater acoustic wireless sensor networks. The proposed circuits realize the same novel method to extract the wake-up call from the acoustic signals received by a sensor node using different circuit topologies. This is accomplished by comparing the amplitude and the duration of the received pulses to a predefined code. A combination of these two parameters provides a safe and robust decoding system. The values and duration of the predefined code can be adjusted by tuning the biasing voltages in the circuits. The main advantages of the presented designs are modularity and tunability. To verify the operation of the proposed system, an ASIC has been realized. The WuRxs have been characterized in terms of tuning, duty cycle, and power consumption. Both WuRxs can consume less than 0.5 $\mu \text{W}$ . Type A occupies an area of 0.058 mm2, has a data rate of 250 bit/s, and presents the lowest power consumption reported, consuming 265 nW and 61 nW in active and sleep modes, respectively.

In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to $90\%$ of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( $V_{th}$ ) or when it approaches the flat band voltage ( $V_{FB}$ ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than $1\%$ . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

In recent years wireless sensor networks (WSNs) have gained significant attention because of their implementation in many different fields. As the nodes in WSNs are typically battery-powered, their lifetime is mainly limited by the sensor nodes power consumption. A typical energy-saving solution consists in implementing wake-up receivers (WuRxs), which are responsible for the sensor node activation only when required. In this work an ultra-low power multivibrator-based WuRx concept is proposed. The WuRx is composed of several input-triggered multivibrators, which generate pulses of fixed duration. These pulses are compared to the input signal through logic gates, which are predefined according to the wake-up call. The sensor node is activated if the codes match. An implementation in TSMC- 180nm CMOS process is proposed and simulated. The WuRx consumes 0.8μW when detecting a 6ms wake-up call signal, and 58. 4pW when in idle mode.