Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as $I_{on}/I_{off}$ , $DIBL$ , and $SS$ , to highlight the advantages and disadvantages of each junctionless transistor category.

Carbon nanotubes (CNTs) can be grown locally on custom-designed CMOS microstructures to use them as a sensing material for manufacturing low-cost gas sensors, where CMOS readout circuits are directly integrated. Such a local CNT synthesis process using thermal chemical vapor deposition (CVD) requires temperatures near 900 °C, which is destructive for CMOS circuits. Therefore, it is necessary to ensure a high thermal gradient around the CNT growth structures to maintain CMOS-compatible temperature (below 300 °C) on the bulk part of the chip, where readout circuits are placed. This paper presents several promising designs of CNT growth microstructures and their thermomechanical analyses (by ANSYS Multiphysics software) to check the feasibility of local CNT synthesis in CMOS. Standard CMOS processes have several conductive interconnecting metal and polysilicon layers, both being suitable to serve as microheaters for local resistive heating to achieve the CNT growth temperature. Most of these microheaters need to be partially or fully suspended to produce the required thermal isolation for CMOS compatibility. Necessary CMOS post-processing steps to realize CNT growth structures are discussed. Layout designs of the microstructures, along with some of the microstructures fabricated in a standard AMS 350 nm CMOS process, are also presented in this paper.

Carbon nanotubes (CNTs) can be locally grown on custom-designed CMOS microheaters by a thermal chemical vapour deposition (CVD) process to utilize the sensing capabilities of CNTs in emerging micro- and nanotechnology applications. For such a direct CMOS-CNT integration, a key requirement is the development of necessary post-processing steps on CMOS chips for fabricating CMOS-MEMS polysilicon heaters that can locally generate the required CNT synthesis temperatures (~650–900 °C). In our post-CMOS processing, a subtractive fabrication technique is used for micromachining the polysilicon heaters, where the passivation layers in CMOS are used as masks to protect the electronics. For dielectric etching, it is necessary to achieve high selectivity, uniform etching and a good etch rate to fully expose the polysilicon layers without causing damage. We achieved successful post-CMOS processing by developing two-step reactive ion etching (RIE) of the SiO₂ dielectric layer and making design improvements to a second-generation CMOS chip. After the dry etching process, CMOS-MEMS microheaters are partially suspended by SiO₂ wet etching with minimum damage to the exposed aluminium layers, to obtain high thermal isolation. The fabricated microheaters are then successfully utilized for synthesizing CNTs by a local thermal CVD process. The CMOS post-processing challenges and design aspects to fabricate CMOS-MEMS polysilicon microheaters for such high-temperature applications are detailed in this article. Our developed process for heterogeneous monolithic integration of CMOS-CNT shows promise for wafer-level manufacturing of CNT-based sensors by incorporating additional steps in an already existing foundry CMOS process.

This article reviews our work on direct integration of carbon nanotubes (CNTs) in MEMS vehicles and shows initial results in realizing direct CNT integration in CMOS. Extraordinary properties of CNTs are fully exploited if they are closely integrated with signal processing electronics. An example device is a CNT-based gas sensor, where CNTs with their huge surface-to-volume ratio act as a very sensitive sensing element, and the CMOS circuits provide the necessary signal processing for a device to give a standardized, calibrated, low-noise output signal. Direct synthesis of CNTs in CMOS will enable wafer-level, low-cost fabrication of CNT-based devices. A major challenge is the 800-1000 °C CNT synthesis temperature requirement, whereas CMOS-compatible temperature is < 300 °C.

In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to $90\%$ of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( $V_{th}$ ) or when it approaches the flat band voltage ( $V_{FB}$ ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than $1\%$ . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.