Zhigang Cai

Dr. Zhigang Cai


Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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25 May 2023 in eClinicalMedicine
Verified
Journal Article
Open access
JLJianwei Liao
Jianwei Liao
YGYu Gui
Yu Gui
ZLZhilin Li
Zhilin Li
ZDZijian Deng
Zijian Deng
XHXianfeng Han
Xianfeng Han
LCLi Chen
Li Chen
Early diagnosis of breast cancer has always been a difficult clinical challenge. We developed a deep-learning model EDL-BC to discriminate early breast cancer with ultrasound (US) benign findings. This study aimed to investigate how the EDL-BC model could help radiologists improve the detection rate of early breast cancer while reducing misdiagnosis. In this retrospective, multicentre cohort study, we developed an ensemble deep learning model called EDL-BC based on deep convolutional neural networks. The EDL-BC model was trained and internally validated on B-mode and color Doppler US image of 7955 lesions from 6795 patients between January 1, 2015 and December 31, 2021 in the First Affiliated Hospital of Army Medical University (SW), Chongqing, China. The model was assessed by internal and external validations, and outperformed radiologists. The model performance was validated in two independent external validation cohorts included 448 lesions from 391 patients between January 1 to December 31, 2021 in the Tangshan People's Hospital (TS), Chongqing, China, and 245 lesions from 235 patients between January 1 to December 31, 2021 in the Dazu People's Hospital (DZ), Chongqing, China. All lesions in the training and total validation cohort were US benign findings during screening and biopsy-confirmed malignant, benign, and benign with 3-year follow-up records. Six radiologists performed the clinical diagnostic performance of EDL-BC, and six radiologists independently reviewed the retrospective datasets on a web-based rating platform. The area under the receiver operating characteristic curve (AUC) of the internal validation cohort and two independent external validation cohorts for EDL-BC was 0.950 (95% confidence interval [CI]: 0.909–0.969), 0.956 (95% [CI]: 0.939–0.971), and 0.907 (95% [CI]: 0.877–0.938), respectively. The sensitivity values were 94.4% (95% [CI]: 72.7%–99.9%), 100% (95% [CI]: 69.2%–100%), and 80% (95% [CI]: 28.4%–99.5%), respectively, at 0.76. The AUC for accurate diagnosis of EDL-BC (0.945 [95% [CI]: 0.933–0.965]) and radiologists with artificial intelligence (AI) assistance (0.899 [95% [CI]: 0.883–0.913]) was significantly higher than that of the radiologists without AI assistance (0.716 [95% [CI]: 0.693–0.738]; p < 0.0001). Furthermore, there were no significant differences between the EDL-BC model and radiologists with AI assistance (p = 0.099). EDL-BC can identify subtle but informative elements on US images of breast lesions and can significantly improve radiologists' diagnostic performance for identifying patients with early breast cancer and benefiting the clinical practice. The 10.13039/501100012166 National Key R&D Program of China .

29 January 2022 in ACM Transactions on Storage
Verified
Journal Article
Open access
JLJun Li
Jun Li
XXXiaofei Xu
Xiaofei Xu
ZCZhigang Cai
Zhigang Cai
JLJianwei Liao
Jianwei Liao
KLKenli Li
Kenli Li
YIYutaka Ishikawa
Yutaka Ishikawa
This article proposes a pattern-based prefetching scheme with the support of adaptive cache management, at the flash translation layer of solid-state drives ( SSDs ). It works inside of SSDs and has features of OS dependence and uses transparency. Specifically, it first mines frequent block access patterns that reflect the correlation among the occurred I/O requests. Then, it compares the requests in the current time window with the identified patterns to direct prefetching data into the cache of SSDs. More importantly, to maximize the cache use efficiency, we build a mathematical model to adaptively determine the cache partition on the basis of I/O workload characteristics, for separately buffering the prefetched data and the written data. Experimental results show that our proposal can yield improvements on average read latency by 1.8 %– 36.5 % without noticeably increasing the write latency, in contrast to conventional SSD-inside prefetching schemes.

1 November 2020 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
JLJun Li
Jun Li
ZSZhibing Sha
Zhibing Sha
ZCZhigang Cai
Zhigang Cai
FTFrancois Trahay
Francois Trahay
JLJianwei Liao
Jianwei Liao

14 December 2022 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
HLHaodong Lin
Haodong Lin
JLJun Li
Jun Li
ZSZhibing Sha
Zhibing Sha
ZCZhigang Cai
Zhigang Cai
YSYuanquan Shi
Yuanquan Shi
JLJianwei Liao
Jianwei Liao
Most flash-based solid-state drives (SSDs) adopt an onboard dynamic random access memory (DRAM) to buffer hot write data. Then, the write or overwrite operations can be absorbed by the DRAM cache, given that there is sufficient locality in the applications’ I/O access pattern, to consequently avoid flushing the write data onto underlying SSD cells. After analyzing typical real-world workloads over SSDs, we observed that the buffered data of small-size requests are more likely to be reaccessed than those of large write requests. To efficiently utilize the limited space of DRAM cache, this article proposes an adaptive request granularity-based cache management scheme for SSDs. First, we introduce a request block corresponding to a write request, as the cache management granularity, and propose a dynamic manner for classifying small and large request blocks. Next, we design three-level linked lists for supporting different routines of upgradation for small and large request blocks, once their data have been hit in the cache. Finally, we present a scheme of evicting the request blocks having the minimum cost in cache replacement, by taking both factors of access hotness and time discounting into account. Experimental results show that our proposal can yield improvements on cache hits and the overall I/O latency by 21.8 % and 14.7 % on average, compared to state-of-the-art cache management schemes inside SSDs.

9 August 2022 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
JWJiaojiao Wu
Jiaojiao Wu
JLJun Li
Jun Li
ZSZhibing Sha
Zhibing Sha
ZCZhigang Cai
Zhigang Cai
JLJianwei Liao
Jianwei Liao
NAND flash-based high-density solid-state drives (SSDs) commonly have limited write endurance, as a single block becomes unavailable after a finite number of program/erase cycles. The (static) wear leveling algorithms migrate cold data to more worn blocks for yielding an even distribution of wears in SSDs. However, migrating cold data must delay normal I/O processing, and unnecessary wear leveling operations may damage SSD endurance as each operation causes a program/erase cycle. This article proposes an adaptive switch on wear leveling (called ASWL), to boost I/O performance and lifetime for high-density SSDs. The basic idea of ASWL is to adaptively switch the threshold function for intelligently triggering wear leveling operations at different stages of SSD lifetime. To this end, we build a mathematical model determining the wear leveling threshold condition with a dynamic manner, by considering the real-time factors of I/O intensity and the wear difference of SSD blocks. Through a series of emulation experiments on several realistic disk traces, we show that the proposed ASWL mechanism can not only greatly improve I/O performance but also noticeably extend the lifetime of high-density SSDs, in contrast to existing wear leveling methods.

21 June 2024 in ACM Transactions on Design Automation of Electronic Systems
Verified
Journal Article
Open access
HTHuanhuan Tian
Huanhuan Tian
JTJiewen Tang
Jiewen Tang
JLJun Li
Jun Li
ZSZhibing Sha
Zhibing Sha
FYFan Yang
Fan Yang
JLJianwei Liao
Jianwei Liao
Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This article builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.