Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.

Radiation-induced soft errors in Integrated Circuits (ICs) have always been a matter of great reliability concern. However, the ongoing shrinking of CMOS technology nodes, which results in high frequency, low power, and small area exacerbates the problem. Thus, accurate evaluation of the ICs’ vulnerability to such errors has become crucial, especially when a radiation-hardening process is developed. In this article, we present a gatelevel Soft Error Rate (SER) estimation framework based on an event-driven approach that models the generated Single Event Transients (SETs) as event pairs that propagate through the circuit. Dynamic Timing Analysis (DTA) is performed to estimate SET arrival times at Flip-Flop (FF) inputs and detect a soft error. Moreover, our approach approximates the glitch height and considers the noise immunity thresholds of gates to evaluate potential SET electrical masking. Additionally, our event-driven framework enables accurate propagation of Single Event Multiple Transients (SEMTs), which have become commonplace in combinational circuits. Experimental evaluation on ISCAS ’89 benchmarks indicates that the proposed event-driven height-aware approach exhibits 21.06% more accurate SER estimation on average, compared to conventional graph-based techniques, with respect to SPICE simulation. F1 scores further strengthen the previous result, demonstrating an average improvement of 11.86%. In terms of failures in time, experimental results show that the graph-based approach overestimates SER by an average of 8558 and up to 16485 errors compared to the proposed method. Finally, our approach is used to effectively identify the most sensitive gates that could potentially be hardened in a SER mitigation scenario.

In contemporary VLSI designs, reliable Soft Error Rate (SER) estimation is critical to ensure circuit reliability under ionizing radiation. Physics-based SER models leverage the inherent linearity of the diffusion equation to construct a discrete representation using the Finite Difference Method (FDM) in three dimensions. However, traditional methods often rely on detailed numerical simulations of these physical processes, resulting in high computational costs and limited scalability across various technological nodes. To accelerate simulation process, in this paper, we propose a compact SER modeling approach based on Moment Matching (MM) combined with the Extended Krylov Subspace (EKS). Experimental results demonstrate significant computational speedups, up to 21×, while maintaining the accuracy of the full model.

The ongoing downscaling of CMOS technology has considerably increased the vulnerability of Integrated Circuits (ICs) to reliability issues, such as Soft Errors and Hardware Trojans (HTs). The combined impact of these threats poses an even more significant challenge to circuit security. The study of the Single Event Multiple Transients (SEMTs) generation and propagation through the circuits constitute the most critical process of the proposed methodology. In particular, a comprehensive layout-based analysis is presented to identify the most impactful regions (grids) in a circuit where HTs can be intentionally injected. Experimental outcomes demonstrate a significant average increase of approximately 32% in the Soft Error Rate (SER) of the utilized ISCAS '89 benchmarks, highlighting the need for a more robust system design to combat reliability-based threats.