The heterogeneous integration underpinned by several advanced packaging options, such as passive interposers offers a promising direction for future integrated systems. However, the diversity of chiplets integrated in these systems can increase design complexity. A means to mitigate this situation is to reuse interposer fabrics. Consequently, reusable interposers should provide for signaling, power, and thermal issues. This work emphasizes thermal issues by introducing a novel and sufficiently accurate thermal monitoring strategy suitable for reusable passive interposers. The proposed strategy is based on metal resistance temperature detectors (RTDs) as sensors optimally arranged on a fixed rectangular grid supporting the reuse of passive interposers. A step-by-step methodology provides the design and allocation of the sensors across the interposer fabric under temperature precision and area constraints. Diverse benchmark scenarios are investigated with the proposed RTDs, which consume only $33.6~\mu \text {W}$ with a footprint of only $0.159~\text {mm}^{2}$ . Simulation results show that the proposed methodology achieves six times ( $6\times $ ) improvement in mean absolute error (MAE) for reconstructed heatmaps over conventional chiplet-based sensors. This improvement is shown for different chiplet placements onto an interposer and for 2.5-D heterogeneous systems, where the integrated components do not include any or sufficient on-chip thermal sensors to provide the required temperature precision.

Stochastic magnetic tunnel junctions (sMTJs) with low energy barriers fluctuate randomly between two resistance states, supplying room‐temperature entropy without pseudo‐random‐number generators. This work develops a device‐faithful sMTJ probabilistic‐bit (p‐bit) model—telegraph switching, a current‐tunable sigmoid response, and Poisson‐distributed dwell times—using literature‐grounded perpendicular‐anisotropy parameters. The p‐bits are integrated into a programmable crossbar whose per‐column accumulation realizes a probability‐domain expectation estimator: the multiply–accumulate is retained as the mean output, while the estimator variance, which scales as over a ‐sample window, provides a calibrated and irreducible measure of uncertainty. A closed‐loop drift self‐calibration scheme re‐biases each cell through a shared digital‐to‐analog converter, turning device volatility from a liability into a managed quantity. A circuit‐level analysis in 22 nm CMOS documents an energy efficiency of up to 869 TOPS/W under a clearly defined read‐phase operation, and an in‐array Monte–Carlo and Bayesian‐uncertainty benchmark quantifies the energy saved by harvesting free thermal entropy instead of CMOS stochastic‐number generators. The architecture is positioned as a sampling accelerator, distinct from stochastic‐computing arithmetic and from coupled Ising machines.

A new approach to end-to-end power delivery for increasingly sought-after hierarchical power delivery units (PDUs) is presented, improving the power efficiency of portable systems. The benefits of the technique are demonstrated through a PDU comprising multiple DC–DC converters, such as low-dropout regulators (LDOs), and the support of heterogeneous loads. A properly tailored Q-algorithm is combined with power gating to manage the power supplied by a multi-level PDU. The effectiveness of the proposed method is evaluated via a realistic PDU for different combinations of loads. The learning-based technique yields up to 13% higher total end-to-end power efficiency in the case of similar loads by utilizing four available LDOs compared to the case of a single LDO, which supports the same span of loads. Moreover, the proposed method improves power efficiency by up to 5% in the case of heterogeneous loads when compared to other autonomous state-of-the-art power management units.

Printed Circuit Board (PCB) thermal monitoring has emerged as necessity for many modern systems, since elevated temperatures can lead to failures. Meanwhile, Infrared (IR) thermography and alternative solutions are impractical for integration with the final product. In this article, a methodology for implementing a planar, copper Resistance Temperature Detector (RTD) array, based on rigid, FR-4 PCB technology, is proposed. The array is utilized to reconstruct in situ thermal maps of a PCB. The proposed 3mm× 3mm sensor (one of the smallest compared to literature) is realized as a serpentine-shaped PCB trace. The onboard measurement circuit is based on a four-wire ratiometric topology, which offers increased accuracy. A high-resolution Analog to Digital Converter (ADC) is employed to measure the resistance of the sensors and analog multiplexers select the sensor to be sampled. The array consists of 64 sensors placed on a hexagonal grid and the complete system occupies 21% of the 150mm× 100mm PCB area. Sensor characterization demonstrates high linearity (R² > 0.9999) and low fit errors (0.12 °C Root Mean Square Error (RMSE)). The resolution of the measurement system is below 0.04 °C at 84.4 °C. A geometry-aware algorithm is developed for reconstructing thermal maps, exhibiting 16% improvement over simple interpolation methods. The experimental results are in agreement with a thermal camera (RMSE as low as 2.8 °C) and the system achieved transient step response rates up to 12.3 °C/s, proving its ability to reconstruct accurate thermal maps.