We report the integration of a ferroelectric (FE) silicon-doped hafnium oxide material in ferroelectric field-effect transistor (FeFET) devices fabricated with an optimized interfacial layer in a gate-first scheme. The effect of increasing the permittivity (k) value of the interface layer on the performance of the metal-ferroelectric-insulator-semiconductor (MFIS)-FE-HfO ₂ FeFET is studied in terms of its switching characteristics, endurance, and retention. In contrast to the previous work, the FE Si:HfO ₂ -integrated FeFET devices show a low-power operation capability as well as an improved endurance characteristics without jeopardizing high-temperature retention. The utilization of an optimized SiON interface layer for MFIS-HfO ₂ FeFET stack is discussed, and the improvements are outlined with reference to a standard low-k SiO ₂ interface.

Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

With the discovery of ferroelectricity in HfO 2 based thin films and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms, the FeFET has emerged from a theoretical dream to an applicable reality. This paper summarizes the status of GLOBALFOUNDRIES FeFET technology and some of its potential applications. We show excellent 0.12µm ² SRAM yields of our mature 28nm CMOS platform, with co-integrated FeFETs, exhibiting a solid memory window of 1.4V. In contrast to conventional embedded memory cells, the FeFET can be integrated like a regular 26Å EOT transistor, exhibiting two reversibly programmable VT states, while offering full design flexibility. We show state of the art across wafer VT variability of the programmed and erased states of the FeFETs and discuss its layout-dependence. Embedded size-competitive FeFETs already allow solid separation of the memory states, approaching a mature 6Sigma distribution. Reasonable endurance and stable data retention are demonstrated. Moreover, an outlook of this technology beyond the von Neumann computing will be discussed, considering some of the various applications of this new, versatile device.

The recent discovery of ferroelectricity in thin film HfO₂ materials renewed the interest in ferroelectric FET (FeFET) as an emerging nonvolatile memory providing a potential high speed and low power Flash alternative. Here, we report more insight into FeFET performance by integrating two types of ferroelectric (FE) materials and varying their properties. By varying the material type [HfO₂ (HSO) versus hafnium zirconium oxide (HZO)], optimum content (Si doping/mixture ratio), and film thickness, a material relation to FeFET device physics is concluded. As for the material type, an improved FeFET performance is observed for HZO integration with memory window (MW) comparable to theoretical values. For different Si contents, the HSO based FeFET exhibited a MW trend with different stabilized phases. Similarly, the HZO FeFET shows MW dependence on the Hf:Zr mixture ratio. A maximized MW is obtained with cycle ratios of 16:1 (HfO₂:Si) and 1:1 (Hf:Zr) as measured on HSO and HZO based FeFETs, respectively. The thickness variation shows a trend of increasing MW with the increased FE layer thickness confirming early theoretical predictions. The FeFET material aspects and stack physics are discussed with insight into the interplay factors, while optimum FE material parameters are outlined in relation to performance.

We report 1-3 bit/cell FeFET operation through optimized HSO and HZO ferroelectric laminate layers using alumina interlayers. Memory window up to 3.5V, switching speed of 300ns, 10 years retention, and 10 ⁴ endurance are reported. The gate stack lamination merits are discussed with insight potential of FeFET as an MLC memory.

The local crystal phase and orientation of ferroelectric grains inside TiN/Hf_0.5Zr_0.5O₂/TiN have been studied by the analysis of the local electron beam scattering Kikuchi patterns, recorded in transmission. Evidence was found that the ferroelectric phase of the layers is derived from an orthorhombic phase, most likely of space group Pca2₁. The orientation analysis reveals a strong out-of-plane texture of the polycrystalline film which is in accordance with a high remanent polarization P_r observed for P-V measurements. The results of this analysis help us to further optimize the ratio of ferroelectric grains and their orientation for many applications, e.g., in the field of emerging memory or infrared sensors.