The formation mechanism of non-recessed Au–free Ohmic contacts on the AlGaN/GaN heterostructures is investigated for various Ti/Al atomic ratios (Al–rich versus Ti–rich) and annealing temperatures ranging from 500 to 950 °C. It is shown that Ti/Al atomic ratio is the key parameter defining the optimum annealing temperature for Ohmic contact formation. Ti–rich contacts processed at high temperature result in low contact resistance ∼0.7 Ω mm, better to those obtained at low temperature or with Al–rich metal stacks. The variation of the contact resistance with Ti/Al atomic ratio and annealing temperature is correlated with the intermetallic phase changes and interfacial reaction. Depending on the Ti/Al atomic ratio, two distinct mechanisms can be distinguished. For a small quantity of Ti (e.g., Al–rich contacts), Ohmic contact formation is done through a weak interfacial reaction which is nonexistent at high temperature due to the degradation of the metal morphology. However, for a quantity of Ti higher than 25 at. % (e.g., Ti–rich contacts), the agglomeration is delayed by 200 °C as compared to Al–rich contacts, and optimal contacts are formed at high temperature through a strong interfacial reaction.

Rapid Thermal Processing (RTP) has been evaluated as an alternative to conventional furnace technique for oxidation of 4H- and 3C-SiC. We show that the growth of the SiO2 films in a RTP chamber is orders of magnitude faster than in a conventional furnace. As well as being fast, this process leads to oxide films with quality comparable or even better than the one grown in classical furnaces. Studying different gas for oxidizing and annealing ambient, we demonstrate that SiO2/SiC interface is significantly improved when using N2O instead of O2 or even N2-O2 dilution.

Wide-bandgap nitride semiconductors are currently in development for high-power electronic applications. Compositional layered heterostructures of such nitrides result in a high polarization field at the interface, enabling a higher electron mobility, a higher power density, and a higher conversion efficiency. Further optimization of such GaN-based high-electron-mobility transistors can be achieved by evolving from a top ${\mathrm{Al}}_x{\mathrm{Ga}}_{1-x}\mathrm{N}$ barrier toward AlN or even ${\mathrm{In}}_y{\mathrm{Al}}_{1-y}\mathrm{N}$ . An ongoing challenge in using such hexagonal nitride semiconductors is the formation of a low-resistive, Au-free, ohmic contact far below $1\mathrm{\Omega }\mathrm{mm}$ . In this paper, we investigate the formation of ohmic contacts by Ti–Al–TiN-based metalization as a function of different annealing temperatures (up to $950{}^{°}\mathrm{C}$ ), Ti–Al ratios (from 15 up to 35 at. %) and nitride barrier composition (${\mathrm{Al}}_x{\mathrm{Ga}}_{1-x}\mathrm{N}$ , GaN, AlN, and ${\mathrm{In}}_y{\mathrm{Al}}_{1-y}\mathrm{N}$ ). Contacts processed on Al_xGa_1–x/GaN, and AlN/GaN heterostructures result in low contact resistance of, respectively, 0.30 and $0.55\mathrm{\Omega }\mathrm{mm}$ , whereas the same contact stack on ${\mathrm{In}}_y{\mathrm{Al}}_{1-y}\mathrm{N}$ results in resistance values of $1.7\mathrm{\Omega }\mathrm{mm}$ . The observed solid-phase reaction of such Ti–Al–TiN stacks were found to be identical for all investigated barrier compositions (e.g., ${\mathrm{Al}}_x{\mathrm{Ga}}_{1-x}\mathrm{N}$ , GaN, AlN, and ${\mathrm{In}}_y{\mathrm{Al}}_{1-y}\mathrm{N}$ ), including the preferential grain alignment to the epitaxial nitride layer. The best performing ohmic contacts are formed when the bottom Ti-layer is totally consumed and when an epitaxially-aligned metal layer is present, either epitaxial Al (for a contact which is relatively Al-rich and annealed to a temperature below $660{}^{°}\mathrm{C}$ ) or ternary ${\mathrm{Ti}}_2\mathrm{AlN}$ (for a relatively Ti-rich contact annealed up to $850{}^{°}\mathrm{C}$ ). The observation that the solid-phase reaction is identical on all investigated nitrides suggests that a further decrease of the contact resistance will be largely dependent on an optimization of the nitride barriers themselves.

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage.