The harmonic suppression performance of active power filter (APF) under model predictive current control is obviously reduced, when the parameter exists a mismatch between the actual value in system and the nominal value adopted in the control. To suppress the influence of parameter mismatching, a model predictive control based on parameter identification with forgetting factor recursive least square (FFRLS) method is proposed for APF. The digital processing procedure of the FFRLS-based APF controller is detailed analyzed and designed. The identification error of inductance between identification value and the actual value is less to 6%, and the total harmonic distortion of grid current is significantly improved, especially a lower value of actual inductance. Simulation and experimental results show that the proposed method can not only effectively eliminate the influence of parameter mismatch on the control, but also result in better steady-state performance while retaining fast dynamic response.

Space vector modulation (SVM) is a mature modulation scheme, which is widely used for voltage source inverters. In this article, a flexible online SVM scheme is proposed for a cascaded H-bridge multilevel inverter (CHMI) under short-circuit and open-circuit switch as well as cell failure conditions. The proposed scheme directly calculates all the active redundant switching states and the dwelling duty cycles of the three space vectors enclosing the reference vector for a CHMI such that balanced line-to-line voltages and currents under failure conditions are generated. Accordingly, the resultant switching sequences are determined to meet any specific requirement, e.g., even-order harmonics elimination and minimization of switching losses. Furthermore, in order to reduce voltage stress on the semiconductors under short- and open-circuit switch conditions, an equal power distribution criterion is introduced. The proposed SVM scheme is fast and independent of the number of levels. Experimental results are presented to demonstrate performance and effectiveness of the proposed scheme.

The dual active bridge (DAB) converter is widely used in renewable energy power generation systems with wide input voltage characteristics. An inappropriate duty cycle will lead to a larger inductor root-mean-square (RMS) current and low efficiency. In this article, an efficiency-oriented optimized triple-phase-shift (OTPS) scheme is proposed for the DAB converter that can reduce the inductor rms current for a wide input voltage and realize zero-voltage switching (ZVS). The ZVS condition contains the direction and amplitude of the inductor current to make the ZVS area more accurate. In addition, the OTPS scheme also has the capability of voltage balancing without additional voltage equalizers under unbalanced load. The influence of deadtime on voltage balance is analyzed and a voltage balancing scheme with compensation of the duty cycle is proposed. To reduce resource occupation and operation time, an online implementation scheme of variable parameter control based on field-programable gate array (FPGA) is proposed. Without a look-up table, the sum of the operation time of the control module and modulation module is only 0.66 $\mu$ s, and the required memory bits are only 459 k. Both operation time and memory bits are reduced by more than 90% compared to the existing literature. Finally, the whole proposed process is verified by the experimental results.

A three-phase to single-phase modular multilevel converter based advanced co-phase traction power supply (MMC-ACTPS) system is an effective structure to address the concerns of phase splitting and poor power quality of the conventional electrified railway. Due to the large number of MMCACTPS system modules, I/O resources and computing speed have high requirements on processors. Moreover, the module capacitor balance is challenging because the sorting time is too long when the traditional sorting algorithm for voltage balance is used. To solve the above issues, a digital implementation scheme of flexible power control strategy for three-phase to single-phase MMC-ACTPS system based on field programmable gate array (FPGA), which has sufficient I/O resources, has been proposed. Due to the parallel execution characteristics of the FPGA, the execution time of the controller and the modulator can be greatly reduced compared with a digital signal processor (DSP) + FPGA or DSpace. In addition, an improved sorting algorithm is proposed to reduce the sorting time and the implementation steps are analyzed. Finally, simulation and experimental results are presented to demonstrate the effectiveness and correctness of the proposed control strategy.

To ensure the voltage-balancing capability of the cascaded H-bridge multilevel rectifier (CHMR), the voltage-balancing space vector pulsewidth modulation (VB-SVPWM) is constructed by combining the minimum energy characteristic. However, the existing voltage balancing modulation strategy could fail under extreme conditions of unbalanced cell loading or when some cells are unloaded due to failure. The power transfer limitations of the sub-cell terminals determine the voltage balancing boundary (VBB) for the VB-SVPWM under several load scenarios. Extension methods are also considered for situations out of this VBB. Following the theoretical derivation and the relationship between the number of no-load cells, the load unbalance index, the number of cascaded cells, the modulation index, and the power factor, a wider VBB can be reconstructed by modifying these above variables. Simulations and experiments are conducted with a three-level, three-cell cascaded rectifier to validate the VBB of the proposed VB-SVPWM and its expansion.

This letter proposes a three-switch ac–dc converter with buck/boost ability, low leakage current, and continuous input/output currents. Therefore, a wide output voltage range and no bulky electromagnetic interference filters can be achieved. Furthermore, the proposed topology can transfer pulsating power, reducing the demand for the output capacitance. Without a complex structure, the total component count is only nine and a high power density can be obtained. In addition, benchmarking is provided to compare various performance aspects with existing topologies. Finally, the validity of the topology is verified by the experimental results.