A SiC double-trench MOSFET embedded with a lower-barrier diode and an L-shaped gate-source in the gate trench, showing improved reverse conduction and an improved switching performance, was proposed and studied with 2-D simulations. Compared with a double-trench MOSFET (DT-MOS) and a DT-MOS with a channel-MOS diode (DTC-MOS), the proposed MOS showed a lower voltage drop (V_F) at I_S = 100 A/cm², which can prevent bipolar degradation at the same blocking voltage (BV) and decrease the maximum oxide electric field (E_mox). Additionally, the gate–drain capacitance (C_gd) and gate–drain charge (Q_gd) of the proposed MOSFET decreased significantly because the source extended to the bottom of the gate, and the overlap between the gate electrode and drain electrode decreased. Although the proposed MOS had a greater R_on,sp than the DT-MOS and DTC-MOS, it had a lower switching loss and greater advantages for high-frequency applications.

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (C_gd) to the gate-to-source capacitance (C_gs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (R_on,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (R_JFET) and the electric field in the gate oxide (E_ox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.

A novel super-junction (SJ) double-trench metal oxide semiconductor field effect transistor (DT-MOS) is proposed and studied using Synopsys Sentaurus TCAD in this article. The simulation results show that the proposed MOSFET has good static performance and a longer short-circuit withstand time (t_sc). The super-junction structure enables the device to possess an excellent compromise of breakdown voltage (BV) and specific on-resistance (R_on,sp). Under short-circuit conditions, the depletion of p-pillar, p-shield, and floating p regions can effectively reduce saturation current and improve short-circuit capability. The proposed device has minimum gate-drain charge (Q_gd) and gate-drain capacitance (C_gd) compared with other devices. Moreover, the formation of floating p regions will not lead to an increase in process complexity. Therefore, the proposed MOSFET can maintain good dynamic and static performance and short-circuit ability together without increasing the difficulty of the process.

A 1.2 kV 4H‐SiC planar power MOSFET with a low‐K dielectric in central gate (LK‐MOS) is proposed in this paper. The LK‐MOS features a P+ shielding region and a thick low‐K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low‐K dielectric, while the depletion layer capacitance is decreased due to the reduced gate‐to‐drain overlap. The LK‐MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF‐FOM ( R _on × C _gd ), and 98.9%, 97.4%, and 69.4% lower HF‐FOM ( R _on × Q _gd ), when compared with that of the conventional MOSFET (C‐MOS), Buffered‐Gate MOSFET (BG‐MOS) and Thick Central Oxide MOSFET (TCOX‐MOS), respectively. Besides, the LK‐MOS can also have 16.8%, 5.9% lower C _gs , and 19.9%, 12.4% lower Q _gs compared with that of BG‐MOS and TCOX‐MOS.

This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance C_gd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM C_gd × R_on,sp and Q_gd × R_on,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications.