Bipolar resistive switching (BRS) cells based on the valence change mechanism show great potential to enable the design of future non-volatile memory, logic and neuromorphic circuits and architectures. To study these circuits and architectures, accurate compact models are needed, which showcase the most important physical characteristics and lead to their specific experimental behavior. If BRS cells are to be used for computation-in-memory or for neuromorphic computing, their dynamical behavior has to be modeled with special consideration of switching times in SET and RESET. For any realistic assessment, variability has to be considered additionally. This study shows that by extending an existing compact model, which by itself is able to reproduce many different experiments on device behavior critical for the anticipated device purposes, variability found in experimental measurements can be reproduced for important device characteristics such as I-V characteristics, endurance behavior and most significantly the SET and RESET kinetics. Furthermore, this enables the study of spatial and temporal variability and its impact on the circuit and system level.

The utilization of bipolar-type memristive devices for the realization of synaptic connectivity in neural networks strongly depends on the ability of the devices for analog conductance modulation under application of electrical stimuli in the form of identical voltage pulses. Typically, filamentary valence change mechanism (VCM)-type devices show an abrupt SET and a gradual RESET switching behavior. Thus, it is challenging to achieve an analog conductance modulation during SET and RESET. Here, we show that analog as well as binary conductance modulation can be achieved in a Pt/HfO₂/TiO_x/Ti VCM cell by varying the operation conditions. By analyzing the switching dynamics over many orders of magnitude and comparing to a fully dynamic switching model, the origin of the two different switching modes is revealed. SET and RESET transition show a two-step switching process: a fast conductance change succeeds a slow conductance change. While the time for the fast conductance change, the transition time, turns out to be state-independent for a specific voltage, the time for the slow conductance change, the delay time, is highly state-dependent. Analog switching can be achieved if the pulse time is a fraction of the transition time. If the pulse time is larger than the transition time, the switching becomes probabilistic and binary. Considering the effect of the device state on the delay time in addition, a procedure is proposed to find the ideal operation conditions for analog switching.

One of the key challenges in the reliability of valence change [valence change-based memory (VCM)] resistive switching random access memories (ReRAMs) is the short-term instability of the programed state. Due to read noise, program verify or shaping algorithms are ineffective and read current (or resistance) distributions always revert to their intrinsic statistics. In this work, we analyze the instability of the high resistive state (HRS) measured on ZrO₂-based devices via Factorial Hidden Markov Models. The extracted current jumps are explained by distinct ionic jumps via physics-based kinetic Monte Carlo (KMC) models. The simulation results reveal jumps of oxygen vacancies from the densely packed filament (plug) region to a sparsely packed gap (disc) region as origin of the most critical, large current jumps. These findings are used to extend our compact model (JART v1b) by a read noise module. We demonstrate simulated HRS instability in excellent agreement with our experimental data. Whereas the KMC approach provides a physical understanding of the processes underlying the HRS instability, the compact model enables the simulation of read noise up to industrially relevant array scales.

Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm’s law and Kirchhoff’s law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

Analog compute schemes as well as compute-in-memory have emerged in an effort to reduce the increasing power hunger of convolutional neural networks, which exceeds the constraints of edge devices. Memristive device types are a relatively new offering with interesting opportunities for unexplored circuit concepts. In this work, the use of memristive devices in cascaded time domain compute-in-memory is introduced with the primary goal of reducing size of fully unrolled architectures. The different effects influencing determinism in memristive devices are outlined together with reliability concerns. Architectures for binary as well as multi-bit multiply and accumulate cells are presented and evaluated. As more involved circuits offer more accurate compute result, a trade-off between design effort and accuracy comes into the picture. To further evaluate this trade-off, the impact of variations on overall compute accuracy is discussed. The presented cells reaches an Energy/OP of 0.23 fJ at a size of 1.2 μm ² for binary and 6.04 fJ at 3.2 μm ² for 4x4 bit multiply and accumulate operations.

The proliferation of machine learning algorithms in everyday applications such as image recognition or language translation has increased the pressure to adapt underlying computing architectures towards these algorithms. Application specific integrated circuits (ASICs) such as the Tensor Processing Units by Google, Hanguang by Alibaba or Inferentia by Amazon Web Services were designed specifically for machine learning algorithms and have been able to outperform CPU based solutions by great margins during training and inference. As newer generations of chips allow handling of and computation on more and more data, the size of neural networks has dramatically increased, while the challenges they are trying to solve have become more complex. Neuromorphic computing tries to take inspiration from biological information processing systems, aiming to further improve the efficiency with which these networks can be trained or the inference can be performed. Enhancing neuromorphic computing architectures with memristive devices as non-volatile storage elements could potentially allow for even higher energy efficiencies. Their ability to mimic synaptic plasticity dynamics brings neuromorphic architectures closer to the biological role models. So far, memristive devices are mainly investigated for the emulation of the weights of neural networks during training and inference as their non-volatility would enable both processes in the same location without data transfer. In this paper, we explore realisations of different synapses build from memristive ReRAM devices, based on the Valence Change Mechanism. These synapses are the 1R synapse, the NR synapse and the 1T1R synapse. For the 1R synapse, we propose three dynamical regimes and explore their performance through different synapse criteria. For the NR synapse, we discuss how the same dynamical regimes can be addressed in a more reliable way. We also show experimental results measured on ZrO_x devices to support our simulation based claims. For the 1T1R synapse, we explore the trade offs between the connection direction of the ReRAM device and the transistor. For all three synapse concepts we discuss the impact of device-to-device and cycle-to-cycle variability. Additionally, the impact of the stimulation mode on the observed behavior is discussed.