The photolithography process is getting more sophisticated with technology node scaling down and VLSI designs becoming complex. As photomask patterns get finer, mask rule checks (MRCs) are inevitable to avoid discrepancies in the layout and to ensure manufacturability. This paper introduces an efficient mask rule checking approach that utilizes a representative edge sampling scheme. The representative edge sampling scheme selects a subset of edges and points of each polygon that capture its contour, meanwhile greatly reducing the number of edges involved in actual checking. Experimental results demonstrate that the proposed approach achieves significant speedup compared with the state-of-the-art academic tool.

As the scale of integrated circuit (IC) design continues to expand, the multi-FPGA system (MFS) is widely employed for logic emulation and simulation acceleration which ensures the functional correctness of logic circuits. During this process, circuit partitioning becomes a dispensable step. In this work, we address the hypergraph modeling techniques for the MFS-orientated circuit partitioning. Firstly, an efficient adaptive flattening algorithm considering multi-dimensional resource constraints and based on dynamic programming (DP) is proposed. Then, a parallel algorithm for clock modeling is proposed. With them, an efficient tool of hypergraph modeling is developed. Experiments on industrial benchmarks with up to sixty million cells have validated the efficiency and correctness of the proposed techniques. The results also demonstrate the benefit of the adaptive flattening to the subsequent hypergraph partitioning, and the significant acceleration effects of the proposed DP-based adaptive flattening and the parallel clock modeling algorithms.

Non-integer multiple cell height (NIMCH) libraries have been adopted by advanced manufacturers in the latest technology node, to offer better power efficiency, performance optimization, and area occupancy. However, in order to meet manufacturing requirements, such as power supply, NIMCH placement must comply with several additional layout restrictions. Currently, the state-of-the-art method applies resynthesis and legalization to the initial placement result to achieve a minimum displacement. However, the two decoupled phases lead to a reduction in the solution space and an insensitivity to timing. Therefore, we propose an iterative algorithm with corresponding data structure, which comprehensively considers displacement and timing information. Experiments demonstrate that our method can generate legalized NIMCH designs with a lower maximum delay and a reduced area.

Mask optimization in lithography is becoming increasingly important as the technology node size shrinks down. Inverse Lithography Technology (ILT) remains one of the most robust and high-performance solutions adopted in industry, yet it suffers from significant computational overhead and complexity. With the growing scale of transistor integration, industry attention has shifted toward improving efficiency and workload scalability. However, most recent academic efforts remain confined to localized pattern restoration regardless of full-chip manufacturing conditions. In this work, we present FuILT-S , a practical full-chip ILT-based mask optimization framework that incorporates sub-resolution assist features (SRAFs) co-optimization to address real-world manufacturing challenges. To enable full-chip scalability, we build a multi-level partitioning strategy following the divide-and-conquer mindset, paired with a workload distribution framework for efficient multi-GPU parallelization. To fix inter-region boundary stitching artifacts, we propose a gradient-fusion technique alongside a multi-level healing strategy. Furthermore, by leveraging rich information from the fused gradient and mask intensity maps, we integrate an SRAF generation module co-optimized with the main layout patterns. Experimental results across different layers from real-world designs demonstrate that FuILT-S is both effective and generalizable. Our framework is open-sourced at https://github.com/OpenOPC/OpenFuILT.