In VLSI design, accurate pre-routing timing prediction is paramount. Traditional machine learning-based methods require extensive data, posing challenges for advanced technology nodes due to the time-consuming data preparation. To mitigate this issue, we propose a novel transfer learning framework that uses data from previous nodes for learning on the target node. Our method initially disentangles and aligns timing path features across different nodes, then predicts each path's arrival time employing a Bayesian-based model capable of handling highly variable arrival time and generalizing to new designs. Experimental results on transfer learning from 130nm to 7nm nodes validate our method's effectiveness.

Non-integer multiple cell height (NIMCH) standard-cell libraries offer promising co-optimization for power, performance and area in advanced technology nodes. However, such non-uniform design introduces new layout constraints where any sub-region can only accommodate gates of the same cell height due to manufacturability concerns. The existing physical design flow for NIMCH circuits, which handles the layout constraint by clustering and relocating gates according to their cell heights, often leads to substantial gate displacement that harms circuit performance. To alleviate the above issue, this paper proposes a row-based logic resynthesis procedure that explicitly adjusts cell heights after initial placement without changing cell positions. Experiment results demonstrate that compared with the conventional NIMCH physical design flow, our proposed approach can reduce the maximal delay by 26.1%.

Non-integer multiple cell height (NIMCH) libraries have been adopted by advanced manufacturers in the latest technology node, to offer better power efficiency, performance optimization, and area occupancy. However, in order to meet manufacturing requirements, such as power supply, NIMCH placement must comply with several additional layout restrictions. Currently, the state-of-the-art method applies resynthesis and legalization to the initial placement result to achieve a minimum displacement. However, the two decoupled phases lead to a reduction in the solution space and an insensitivity to timing. Therefore, we propose an iterative algorithm with corresponding data structure, which comprehensively considers displacement and timing information. Experiments demonstrate that our method can generate legalized NIMCH designs with a lower maximum delay and a reduced area.