Not all computing problems are created equal. The inherent complexity of processing certain classes of problems using digital computers has inspired the exploration of alternate computing paradigms. Coupled oscillators exhibiting rich spatio-temporal dynamics have been proposed for solving hard optimization problems. However, the physical implementation of such systems has been constrained to small prototypes. Consequently, the computational properties of this paradigm remain inadequately explored. Here, we demonstrate an integrated circuit of thirty oscillators with highly reconfigurable coupling to compute optimal/near-optimal solutions to the archetypally hard Maximum Independent Set problem with over 90% accuracy. This platform uniquely enables us to characterize the dynamical and computational properties of this hardware approach. We show that the Maximum Independent Set is more challenging to compute in sparser graphs than in denser ones. Finally, using simulations we evaluate the scalability of the proposed approach. Our work marks an important step towards enabling application-specific analog computing platforms to solve computationally hard problems.

In this work, we experimentally demonstrate an integrated circuit (IC) of 30 relaxation oscillators with reconfigurable capacitive coupling to solve the NP-Hard Maximum Cut (Max-Cut) problem. We show that under the influence of an external second-harmonic injection signal, the oscillator phases exhibit a bi-partition which can be used to calculate a high quality approximate Max-Cut solution. Leveraging the all-to-all reconfigurable coupling architecture, we experimentally evaluate the computational properties of the oscillators using randomly generated graph instances of varying size and edge density (ƞ). Further, comparing the Max-Cut solutions with the optimal values, we show that the oscillators (after simple post-processing) produce a Max-Cut that is within 99% of the optimal value in 28 of the 36 measured graphs; importantly, the oscillators are particularly effective in dense graphs with the Max-Cut being optimal in 7 out of 9 measured graphs with ƞ=0.8. Our work marks a step towards creating an efficient, room-temperature-compatible non-Boolean hardware-based solver for hard combinatorial optimization problems.

This paper presents a RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression logic (SDLS) style. Together with a custom adaptive clock generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully-integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments. At the nominal core VDD of 0.6V, the core can scale its performance from 6nW at 11Hz operating frequency to 140nW at 8.2kHz operating frequency. Across the supply voltage range, the core is capable of delivering minimum power of 840pW, maximum frequency of 41.5kHz, and a minimum energy of 13.4pJ/cycle.

On-chip oscillators are popular clocking solutions for a wide range of circuits and systems due to their ease of integration and low form factor, but their energy efficiency is typically limited to the pJ/cycle range by a number of contributors, such as active biasing currents, frequency dividers, and comparators. This work presents an on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts. A test chip is implemented in 65-nm CMOS and achieves 18.8 fJ/cycle (10.5 nW at 560 kHz) while maintaining an average steady-state temperature stability of 96.1 ppm/°C from 0 °C to 100 °C.

This work presents a 640 pW, 22 pJ/conversion gate leakage-powered temperature sensor with 0.25°C resolution and -2.7/1.8°C worst-case inaccuracy from - 20 °C to 100°C. Gate leakage currents drive both the sensing and sampling elements to provide compact but reliable operation that balances low power and low energy for flexible application use. This low-power, low-energy performance enables continuous sub-nW temperature sensing for the Internet of Things.

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0-40°C. The TC increases to 4.3 ppm/°C over the range from -15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 μW with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of 8 μs by employing a voltage buffer to quickly stabilize the voltage reference.