In this letter, 600-V normally-OFF SiN_x/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) is reported. Normally-OFF operation and low OFF-state gate leakage are obtained by using fluorine plasma ion implantation in conjunction with the adoption of a 17-nm SiN_x thin film grown by plasma-enhanced chemical vapor deposition as the gate insulator. The normally-OFF MIS-HEMT exhibits a threshold voltage of +3.6 V, a drive current of 430 mA/mm at a gate bias of 14 V, a specific ON-resistance of 2.1 mΩ·cm² and an OFF-state breakdown voltage of 604 V at a drain leakage current of 1 μA/mm with V_GS=0 V, and the substrate grounded. Effective current collapse suppression is obtained by AlN/SiN_x passivation as proved by high-speed pulsed I-V and low-speed high-voltage switching measurement results.

We report an in situ low-damage pre-gate treatment technology in an atomic layer deposition (ALD) system prior to the ALD- Al₂O₃ deposition, to realize high-quality Al₂O₃/III-nitride (III-N) interface. The technology effectively removes the poor quality native oxide on the III-N surface while forming an ultrathin monocrystal-like nitridation interlayer (NIL) between Al₂O₃ and III-N surface. With the pre-gate treatment technology, high-performance Al₂O₃(NIL)/GaN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors are demonstrated, exhibiting well-behaved electrical characteristics including suppressed gate leakage current, a small subthreshold slope of ~64 mV/dec, and a small hysteresis of ~0.09 V.

A low on-resistance normally-off GaN double-channel metal-oxide-semiconductor high-electronmobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with Vth of +0.5 V at ^I DS = 10 μA/mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm ² /(V·s). The on-resistance is as small as 6.9 Q·mm for a DC-MOS-HEMT with LG/LGS/ ^L GD = 1.5/2/15 μm, and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. Index Terms-Double-channel MOS-HEMT (DC-MOSHEMT), field-effect mobility, gate recess, normally-off.

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.

We demonstrate high-voltage depletion-mode and enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) platform. The GaN-on-SOI wafer features GaN epilayers grown by metal-organic chemical vapor deposition on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer. Micro-Raman spectroscopy significantly reveals reduced stress in the GaN epilayers, which is a result expected from the compliant SOI substrate. E-mode HEMTs fabricated by fluorine plasma implantation technique deliver high on/off current ratio (10⁸-10⁹), large breakdown voltage (1471 V with floating substrate), and low on-resistance (3.92 mΩ·cm²).