The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance R _ON and threshold voltage V _TH are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic R _ON is found to exhibit different dependence on the gate drive voltage V _GS from the static R _ON . While reasonably suppressed at higher V _GS of 5 and 6 V, the degradation in dynamic R _ON is significantly larger at lower V _GS of 3-4 V, which is attributed to the positive shift in V _TH under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the V _TH shift on the dynamic R _ON ; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices.

Enhancement-mode (E-mode) buried p-channel GaN metal-oxide-semiconductor field-effect-transistors (p-GaN-MOSFET's) with threshold voltage (V _TH ) of -1.7 V, maximum ON-state current (I _ON ) of 6.1 mA/mm and I _ON /I _OFF ratio of 10 ⁷ are demonstrated on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. An oxygen plasma treatment (OPT) was deployed to the gated p-GaN region where a relatively thick (i.e. 31 nm) GaN is retained without aggressive gate recess. The OPT converts the top portion of the GaN layer to be free of holes so that only the bottom portion remains p-type while being spatially separated from the etched GaN surface and gate-oxide/GaN interface. As a result, E-mode operation is enabled while a high-quality p-channel is retained. Multi-energy fluorine ion implantation was implemented for planar isolation of GaN p-channel FETs with mesa edges and sidewalls eliminated. Consequently, high I _ON /I _OFF ratio is obtained.

The planar nature of the GaN heterojunction devices provides extended dimensions for implementing monolithic power integrated circuits. This article presents a comprehensive review of the advancements in GaN power integration. Basic building blocks in a power integration platform based on p-GaN gate HEMT technology are discussed, including high-and low-voltage transistors, lateral field-effect rectifiers, resistors, and capacitors. Exemplary designs of monolithic gate driving circuit and detection/protection circuits based on this platform are demonstrated. Technologies to address other challenges, including the lack of mature complementary logic (CL) and the substrate-induced crosstalk effect, are also demonstrated. More forward-looking development of power integration based on wide bandgap semiconductors is also presented in a hybrid GaN/SiC field-effect transistor that is expected to harness the complementary merits of GaN and SiC, and ON-chip GaN-based nonvolatile memory device that could provide versatile intelligence.

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type p-GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current-voltage (I-V) characteristics and threshold voltage (VTH) instability of p-GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the p-GaN layer would promote the formation of defect levels near the metal/ p-GaN interface, leading to the initial p-GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.