This letter proposes a dual-band high-efficiency rectifier using a GaN transistor. Positive polarity and negative polarity modes are set at $f_{1}$ , and $f_{2}$ , respectively. Then, the rectifier operation at $f_{1}$ and $f_{2}$ is realized upon adjusting only the phase of the corresponding feedback loop. This releases the limitation that the original power amplifier (PA) must be dual-band operation. In addition, class-F harmonic control theory is used to enhance efficiency. Moreover, the proposed technique has no frequency dependence and can be used to achieve arbitrary frequency ratios. To verify the effectiveness of the proposed method, a high-efficiency rectifier operating at 1.9 and 2.4 GHz is designed and fabricated using a CGH40010F GaN HEMT. Measurements illustrate that the implemented rectifier can realize an efficiency of over 75% at 1.9 GHz and 2.4 GHz when an input power of 40 dBm is applied and the dc load is $70~\Omega $ . Also, the size of circuit is only 4.7 cm $\times3.4$ cm.

This paper provides a concise overview of recent developments in sparse antenna arrays, with a specific focus on techniques for reducing mutual coupling. It explores the concept and definitions of sparse arrays in different applications, highlighting their historical significance in antenna theory. The paper addresses the mutual coupling problem and presents reduced coupling geometrical configurations through illustrative examples. Various mutual coupling compensation techniques are discussed. The paper conducts a comprehensive comparison of multiple array design optimisation techniques, including genetic algorithm, covariance matrix adaptation evolution strategy, particle swarm optimisation, trust-region framework, Nelder-Mead simplex algorithm, interpolated Quasi-Newton, and classic Powell. The comparison emphasizes achieving desired radiation performance and evaluates the mutual coupling coefficient using 4×4 planar arrays and 16×1 linear arrays with typical patch antennas in the mmWave bands. Notably, the paper considers optimised non-uniform antenna element positioning within the arrays, which has shown promising results in reducing mutual coupling. The study also introduces the application of beam steering to these optimised non-uniform arrays, demonstrating resilience to beam steering degradation and potential performance improvements. The findings indicate that particle swarm optimisation generally provides the most consistent performance across the discussed optimisation problems.

This paper proposes a technique which allows quadband impedance matching and impedance level shifting Doherty power amplifier (DPA) design. By using novel coupler networks with reactance and choosing appropriate complex load impedances, the quadband DPA can reach a power back-off range (OBO) of over 9 dB. In addition, the peak PA branch and the carrier PA branch use different coupler network parameters in order to satisfy different impedance requirements. To illustrate the design procedure a quadband DPA with 9 dB OBO operating in 0.5-0.7 GHz, 1.5-1.7 GHz, 2.5-2.7 GHz, and 3.5-3.7 GHz frequency ranges is designed, fabricated and tested. Measurements demonstrate that the DPA can deliver saturated output power between 43.1 dBm and 43.8 dBm in all four bands, with a drain efficiency ranging from 63.3% to 66.5%. Also, drain efficiency of from 42.2% to 52.3 % can be obtained at an OBO of 9 dB level. The DPA implemented here shows state-of-the-art performance for OBO under quad-band operation.

This brief proposes a novel power amplifier (PA) topology which can realize PA operation with high power back-off range (OBO) and wide bandwidth. Here a short-circuit reactance instead of an additional PA branch is introduced into the isolated port of a coupler to provide the frequency dependency required for broadband load impedance modulation. In addition, the corresponding complex load impedances at each normalized frequency are given to achieve high OBO based on the use of the same transistor in both the carrier PA and peak PA branches. The behaviors of the proposed PA as a function of input power are also derived based on the appropriate complex load impedance. To validate the proposed topology, a PA with 9 dB OBO operating across 1.0-3.0 GHz is designed, fabricated, and tested. Measurements illustrate that the PA can deliver a saturated output power from 44 dBm to 45 dBm over 1.0-3.0 GHz, with a drain efficiency ranging from 62% to 71%. Drain efficiencies are from 41% to 48% at the OBO of 9 dB.

An analog/digital hybrid delay-locked-loop (DLL) phase conjugator (PC) for use in retrodirective array (RDA) applications is proposed, implemented, and measured. Compared with previous phase-locked-loop PC solutions, the proposed DLL PC has a number of unique features that make it superior to previous solutions in many applications. These features include: 1) the ability to hold the phases of conjugated outputs even when input pilots disappear; 2) the ability to track the changing rate of phases of input pilots even when the pilot signals with dynamic phases disappear for a short period of time, i.e., the implemented RDAs can constantly track a moving target for retransmission even when the incoming pilots are not available due to deep channel fading or time division duplex operation; 3) the DLL PC can be flexibly configured as the voltage-controlled phase shifters for the use in traditional phased beam-steering arrays; 4) the DLL PC can indicate direction of arrival of the incoming signals without recourse to any baseband algorithms; and 5) the DLL PC is unconditionally stable. The operation of the DLL PC is articulated in this paper, and prototypes are built and their performance and functions are tested. In addition, a K-/Ka-band RDA demonstrator for satellite communications, based on the proposed DLL PC architecture, is implemented and measured, validating the "retro-direct" functionality over a wide view angle. To the best of our knowledge, this is the first time that a DLL has been used for PC, and it is the first time that a K-/Ka-band RDA based on this technology has been experimentally demonstrated.

An extremely simple, low‐cost, chipless RFID reader is demonstrated. The reader consists of only a single voltage controlled oscillator (VCO) as the detector front end. The information from the chipless RFID tag appears as a low‐frequency variation on the VCO DC bias supply which is readily detected and demodulated. Experimental results are shown for successful detection of a 10‐bit RFID tag, operating over the frequency range 2.4–3.4 GHz. The results when compared with those taken from a vector network analyser (VNA) prove that the VCO detector can provide a similar level of performance to the more sophisticated VNA arrangement. The proposed solution provides a significant simplification of the chipless RFID reader.