Aoming Zhan

Aoming Zhan

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Aoming Zhan

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

Research Focus & Metrics

Academic Career Length

2Years (2025-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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15 August 2025 in IEEE Transactions on Circuits and Systems II: Express Briefs
Verified
Journal Article
Closed access
LClong chen
long chen
YZYe Zhao
Ye Zhao
ZWZiyuan Wang
Ziyuan Wang
AZAoming Zhan
Aoming Zhan
JGJinyu Gao
Jinyu Gao
SQShushan Qiao
Shushan Qiao
The relentless growth of artificial intelligence of things (AIoT) applications has tightened sub-milliwatt powerbudget constraints on embedded vision systems. To address this challenge, this brief presents the first brain-inspired intelligent vision sensor (BIVS) based on a novel spiking processing-insensor (PIS) architecture that efficiently converts captured pulsewidth-modulation (PWM) image data into real-time sparse spike features for subsequent intelligent processing, offering an attractive balance between computational accuracy and energy efficiency. A 126 126 BIVS is designed in 180nm CMOS technology and consumes 66.9μJW at 661fps with a resulting efficiency of 5.02 TOPS/W and FoM of 6.37 pJ/pixel/frame. It also achieves a spike feature map accuracy of 99.73% on the MNIST dataset and a classification accuracy of 99.05% when coupled with a simplified spiking convolutional neural network (SCNN).

28 April 2026 in IEEE Solid-State Circuits Letters
Verified
Journal Article
Closed access
AZAoming Zhan
Aoming Zhan
YZYe Zhao
Ye Zhao
YZYulin Zhang
Yulin Zhang
GHGengchen Han
Gengchen Han
QJQihang Jiang
Qihang Jiang
SQShushan Qiao
Shushan Qiao
With the growing demand for energy-efficient convolutional neural network (CNN) accelerators in edge intelligence, conventional digital CNN processors with fixed precision incur excessive switching energy and limited scalability. This work presents a time-domain CNN (TD-CNN) engine that achieves adaptive precision and computation reduction for ultra-low-power operation. The main features include: 1) A dual-precision mode-switching DTC (DPMS-DTC) supporting both low-power and high-linearity modes. 2) A bit-sliced hybrid-precision (BSHP) MAC computing technique that achieves high accuracy with low power consumption. 3) A threshold-controllable near-negative prediction (TCNNP) technique aimed at reducing redundant MAC operations. Fabricated in a 55-nm CMOS process, the engine achieves 28.7–412.5 μW power consumption and a 255.7-993.3 TOPS/W figure-of-merit. It delivers 92.10%–90.91% CIFAR-10 accuracy using 6-bit inputs and weights. With a 1% accuracy allowance, TCNNP reduces MAC operations by 59%.

1 January 2026 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
LClong chen
long chen
YZYe Zhao
Ye Zhao
YRYUMENG REN
YUMENG REN
JGJinyu Gao
Jinyu Gao
AZAoming Zhan
Aoming Zhan
SQShushan Qiao
Shushan Qiao