This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO ₂ , and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 μ A maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3–5.7 μ W AFE power and 1.52 mm ² die area with 102dB (SpO ₂ mode), 110–116 dB (HR & PTT mode) dynamic range. A SpO ₂ test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 μ W and 43.7 μ W system power, respectively.

This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub- μ W wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance (ΔC), excluding baseline and parasitic capacitances. The experimental results show the measurement range of ΔC are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 μ W for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 mm ² of active area (0.0251 mm ² /Ch).