Wake-up receivers (WuRXs) offer a potentially energy-efficient means to enable asynchronous wake-up of higher-power and higher-performance radios without needing frequent (often energy-expensive) synchronization. Since WuRXs are typically on for a large percentage of the time, keeping their power consumption very low is critical to minimizing total energy draw. However, this is difficult while maintaining good sensitivity, interference resiliency, and robustness, all with application-appropriate wake-up latencies and form factors. This article reviews the main challenges facing WuRXs, outlines the most popular WuRX architectures, and details essential design techniques and trade-offs towards enabling utility in emerging applications.

This article presents a highly integrated 2.4-GHz wake-up receiver (WuRX) achieving 91.5 dBm sensitivity with a state-of-the-art power and latency combination of 2 $\mu \text{W}$ at 100 ms. The proposed within-packet duty-cycling method employs a carrier-sense mechanism to turn off the WuRX early under idle channel conditions, which reduces the dc-power compared with conventional asynchronous packet-level duty cycling by $9\times $ at 10 ms latency (21 $\mu \text{W}$ ) and $2\times $ at 1 s latency (0.9 $\mu \text{W}$ ) at the cost of 2 dB in sensitivity. The uncertain-IF topology with a phase-locked loop (PLL)-aided event-driven calibrated local-oscillator (LO) helps reduce the dc-power while maintaining a fast startup. The channel-embedded OOK scheme is used to create a deterministic IF to enable baseband (BB) channel selection and achieve continuous wave (CW) interference tolerance of −47 dB at 20 MHz offset. Fabricated in 65 nm CMOS, input matching and $LC$ oscillator are all implemented on-chip, and operation is demonstrated with integrated low dropout regulators to capture the degradations in realistic system integration.

In this article, we present the design and analysis of a 785-nW multimodal sensor interface IC for ozone pollutant sensing and correlated cardiovascular disease monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The proposed hybrid dc offset current cancellation (DCOC) along with a 4- MΩ gain-regulated cascode transimpedance amplifier (RGC-TIA) enable PPG readout power reduction by 37×, compared with the state-of-the-art PPG sensor interfaces. The ozone sensing channel proposes an adaptive architecture to enable low V _DD operation, achieving a 300× power reduction, compared with the state-of-the-art gas sensing readouts. The ozone sensing channel's performance was also verified using custom resistive metal-oxide sensors for concentrations from 50 to 900 ppb. The sensor interface IC is fabricated in a 65-nm CMOS, integrating a 165-nW voltage-mode ECG channel, a 532-nW current-mode PPG channel, 76-nW resistive-mode ozone channel, and 12.6-nW peripheral circuits, all at 0.6 V. The total system power consumption including the LED and a custom digital readout IC is 10.98- 15.51 μW, which is 41×- 57× less than prior ozone/CVD joint monitoring sensor interface systems.

On-chip oscillators are popular clocking solutions for a wide range of circuits and systems due to their ease of integration and low form factor, but their energy efficiency is typically limited to the pJ/cycle range by a number of contributors, such as active biasing currents, frequency dividers, and comparators. This work presents an on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts. A test chip is implemented in 65-nm CMOS and achieves 18.8 fJ/cycle (10.5 nW at 560 kHz) while maintaining an average steady-state temperature stability of 96.1 ppm/°C from 0 °C to 100 °C.