Rishika Agarwala

Rishika Agarwala

Auto-generated profile, based on publicly available information

Rishika Agarwala

Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA

Research Focus & Metrics

Academic Career Length

8Years (2019-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
12 February 2021 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Closed access
RARishika Agarwala
Rishika Agarwala
PWPeng Wang
Peng Wang
HBHenry L. Bishop
Henry L. Bishop
ADAnjana Dissanayake
Anjana Dissanayake
BCBenton H. Calhoun
Benton H. Calhoun
In this article, we present the design and analysis of a 785-nW multimodal sensor interface IC for ozone pollutant sensing and correlated cardiovascular disease monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The proposed hybrid dc offset current cancellation (DCOC) along with a 4- MΩ gain-regulated cascode transimpedance amplifier (RGC-TIA) enable PPG readout power reduction by 37×, compared with the state-of-the-art PPG sensor interfaces. The ozone sensing channel proposes an adaptive architecture to enable low V DD operation, achieving a 300× power reduction, compared with the state-of-the-art gas sensing readouts. The ozone sensing channel's performance was also verified using custom resistive metal-oxide sensors for concentrations from 50 to 900 ppb. The sensor interface IC is fabricated in a 65-nm CMOS, integrating a 165-nW voltage-mode ECG channel, a 532-nW current-mode PPG channel, 76-nW resistive-mode ozone channel, and 12.6-nW peripheral circuits, all at 0.6 V. The total system power consumption including the LED and a custom digital readout IC is 10.98- 15.51 μW, which is 41×- 57× less than prior ozone/CVD joint monitoring sensor interface systems.

3 May 2019 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Open access
NLNingxi Liu
Ningxi Liu
RARishika Agarwala
Rishika Agarwala
ADAnjana Dissanayake
Anjana Dissanayake
DTDaniel S. Truesdell
Daniel S. Truesdell
SKSumanth Kamineni
Sumanth Kamineni
BCBenton H. Calhoun
Benton H. Calhoun
This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0-40°C. The TC increases to 4.3 ppm/°C over the range from -15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 μW with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of 8 μs by employing a voltage buffer to quickly stabilize the voltage reference.

30 January 2024 in IEEE Transactions on Biomedical Circuits and Systems
Verified
Journal Article
Closed access
PWPeng Wang
Peng Wang
RARishika Agarwala
Rishika Agarwala
NONatalie B. Ownby
Natalie B. Ownby
XLXinjian Liu
Xinjian Liu
BCBenton H. Calhoun
Benton H. Calhoun
This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO 2 , and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 μ A maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3–5.7 μ W AFE power and 1.52 mm 2 die area with 102dB (SpO 2 mode), 110–116 dB (HR & PTT mode) dynamic range. A SpO 2 test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 μ W and 43.7 μ W system power, respectively.