The withstand capability and threshold voltage (VTH) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer I-V characteristics and gate-to-source leakage current (I _GSS ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations (t _p ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be ~3.3 μs. V _TH instability under repetitive SC tests prior to the device failure is characterized. A bidirectional V _TH shift behavior, i.e., negative shift at shorter t _p and positive shift at longer t _p , was revealed. The V _TH shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex V _TH shift behavior are explained in a unified framework by taking into account the junction temperature (T _j ) increase with longer t _p . TCAD device simulation is used to help analyze the mechanisms.

Short circuit (SC) capability of 650-V Schottky-type p -GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability.

Short circuit capability of commercial SiC MOSFETs is analyzed, which is compared with that of commercial Si IGBTs. Junction temperatures during short circuit tests are analyzed in this work. A test bench is designed for short circuit tests of discrete MOSFETs and IGBTs. Commercially available 1200V SiC MOSFETs from Wolfspeed (C2M0080120D) and 1200V Si IGBTs from Infineon (IKW25N120H3) with similar current rating are tested. The short circuit withstand time (t_cr) of the 1200V SiC MOSFET is much shorter than that of the 1200V Si IGBT. A 1-D transient finite element thermal model based on structure parameters is constructed to investigate the junction temperature curves during short circuit. According to the analysis of heat generation, short circuit capability of the SiC MOSFET is mainly restricted by high electric field at the P-N junction and high short circuit current density.

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally-off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si-mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on-state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems.

GaN ${p}$ -channel field-effect transistors ( ${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage ( ${V}_{\mathrm {TH}}$ ) instability of ${p}$ -channel GaN MOSFETs with Al ₂ O ₃ as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$ .