In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type p-GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current-voltage (I-V) characteristics and threshold voltage (VTH) instability of p-GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the p-GaN layer would promote the formation of defect levels near the metal/ p-GaN interface, leading to the initial p-GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

In this work, the deep-level transient spectroscopy (DLTS) is conducted to investigate the gate stack of the p-GaN gate HEMT with Schottky gate contact. A metal/p-GaN/AlGaN/GaN heterojunction capacitor is prepared for the study. The DLTS characterization captures the transient capacitance change in the stack, from which the capacitance of the metal/p-GaN Schottky junction can be extracted. By proper selection of the rate window, the impacts of the hole insufficiency effect are avoided during trap states evaluation. Thus, the information of deep energy levels in the p-GaN layer is revealed, which consists of an electron trap state with activation energy of 0.85 eV and a hole trap state with activation energy of 0.49 eV. The identification of these trap states in the p-GaN layer provides a physical foundation for understanding the threshold voltage instability in Schottky-type p-GaN gate power HEMTs.

The withstand capability and threshold voltage (VTH) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer I-V characteristics and gate-to-source leakage current (I _GSS ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations (t _p ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be ~3.3 μs. V _TH instability under repetitive SC tests prior to the device failure is characterized. A bidirectional V _TH shift behavior, i.e., negative shift at shorter t _p and positive shift at longer t _p , was revealed. The V _TH shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex V _TH shift behavior are explained in a unified framework by taking into account the junction temperature (T _j ) increase with longer t _p . TCAD device simulation is used to help analyze the mechanisms.

Commercially available normally-off GaN power HEMT devices have typically adopted a p-GaN gate structure. In the gate region, there exist a Schottky junction and a p-GaN/AlGaN/GaN heterojunction. With drain voltage changing during a switching process, the variation of net charge in the floating p-GaN layer would cause instability in threshold voltage. Besides, the gate-related junction capacitances would exhibit behavior different from those of a Si MOSFET. Consequently, the switching transient performance of a GaN transistor with a p-GaN gate could be significantly influenced by the aforementioned factors. In this work, the threshold voltage instability associated with the drain-to-gate voltage stress is firstly analyzed. Despite the difficulties in directly performing capacitance measurements inside the device structure, a hybrid physical-behavior modeling method is proposed. The model is capable of extracting the capacitance-bias relationships with regard to the gate region from static terminal measurements. In previous works, the advanced analytical model would make modest change on Si MOSFET's model. As a result, the simulated waveforms would exhibit 20$\times$50% discrepancy from experiment. In contrast, the proposed switching transient analytical approach would exhibit improved accuracy. Consequently, the switching transient performance of GaN transistor with p-GaN gate could be more accurately evaluated.

The dynamic on-resistance ( r _ON ) of two mainstream 600 V/650 V p -GaN gate power high-electron-mobility transistors (HEMTs) with Ohmic- and Schottky-type p -GaN gate contacts are characterized under the hard-switching condition and show strong dependences on the gate driving conditions under both double-pulse and multipulse testing modes. The statistical measurement of multiple samples indicates this is a representative phenomenon in these two types of commercial p -GaN gate power HEMTs. For Ohmic-type p -GaN gate HEMT, gate injection current ( I _G ) at the on state from the p -GaN gate facilitates a faster detrapping process and contributes to a smaller dynamic r _ON . For Schottky-type p -GaN gate HEMT, the dynamic r _ON shows a strong dependence on the gate overdrive voltage ( V _GS ) because the higher V _GS can compensate the increase in dynamic r _ON induced by the positively shifted V _TH under high drain bias. A larger I _G (from 1.2 to 22 mA) and higher V _GS (from 5 to 7 V) play the most important role in suppressing the dynamic r _ON under high switching frequency and high drain bias condition (i.e., 400 kHz/400 V), where the reduction of dynamic r _ON is 13.6% and 17.1% for Ohmic-type and Schottky-type p -GaN gate HEMTs, respectively.