This article reports an energy/area-efficient zoom capacitance-to-digital converter (CDC)-based CMOS humidity sensor. It achieves the best-in-class error of $\pm$ 0.8%RH and better figure of merit (FoM $_{w}$ ; 87 fJ/c.step) than the state-of-the-art humidity sensors due to the use of the two techniques described in the following: 1) a charge-redistribution correlated level-shifting (CR-CLS) floating inverter amplifier (FIA) is proposed to increase the conventional CLS-FIA open-loop gain by at least 13.5 dB across temperature variations ( $-$ 40 $^{\circ}$ C to 85 $^{\circ}$ C) and the extreme process corners, minimizing the closed-loop FIA gain error and thus the CDC nonlinearity and humidity error and 2) a pair of stacked humidity sensors over the circuits, all of which are included in the standard CMOS process, is proposed to achieve a lower cost and decrease the area by half. The proposed CMOS humidity sensor is implemented in a 55-nm CMOS process. The measurement results show that the capacitance resolution and humidity resolution are 197 aF and 0.094%RH, respectively, at a total input capacitance of 3 pF, and the effective number of bits (ENOB) is 12.1 at a clock frequency of 2.5 MHz and a cycle number per conversion (N) of 16. The proposed humidity sensor consumes 9.57 $\mu $ W at the conversion time of 0.04 ms. The sensor exhibits a $\pm$ 0.8%RH peak-to-peak accuracy (3 $\sigma $ error of 2.5%RH) among 40 chips from 20%RH to 85%RH.

This brief introduces a single-ended SAR ADC with a novel fully differential DAC switching scheme. This scheme achieves fully differential switching by smartly sampling the single-ended input and pre-switching before the conversion phase, maintaining a constant DAC output common-mode voltage during conversion. As a result, it eliminates the impact of comparator dynamic offset voltage on SAR ADC precision. Additionally, this switching scheme does not require additional reference voltages like Vcm, which reduces system complexity and peripheral circuit power consumption. The prototype is fabricated using a 110 nm CMOS process and tested with a 1 V supply voltage and 200 kHz sampling rate. The measured ENOB is 10.1 bits with a near Nyquist input frequency, resulting in a Walden figure-of-merit (FoM) of 31 fJ/conversion step.