The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V V _DD . For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of ~4800/h, with an active power of 1.68 $\mu \text{W}$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at ~720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

This article presents a fully dynamic scalable switched-capacitor delta-sigma modulator that achieves a 94.1-dB dynamic range (DR). Power-and- bandwidth scalability by only changing the clock frequency is achieved using a capacitively biased and swing-enhanced floating inverter operational transconductance amplifier (OTA). Fabricated in a 180-nm CMOS process, the prototype achieves an signal-to-noise-and-distortion ratio (SNDR) of >87 dB across 4x scaling from 100 to 400 kHz of the sampling frequency $f_{{S}}$ . At 200-kHz $f_{{S}}$ , it achieves an SNDR/DR of 89.3/94.1 dB while consuming 4 μW, leading to a DR-based Schreier figure of merit (FoM) of 177.1 dB.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $\Delta \Sigma \text{M}$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $\Delta \Sigma \text{M}$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $\mu \text{m}$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $\mu \text{W}$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH ² , which is more than six times better than the state of the art.

This article presents a fully dynamic 2–0 multistage noise-shaping (MASH) analog-to-digital converter (ADC) for low-power and high-precision applications. It implements the feedforward digitally with a 3-bit asynchronous successive-approximation-register (SAR) ADC and reuses it as the zeroth backend stage. Correlated level shifting (CLS) boosts the floating inverter amplifier (FIA) gain, embedded in the loop filter to implement integration. Dynamic body-biasing (DBB) technique helps boost the gain of a single-stage FIA with only one reservoir capacitor. Fabricated in 55-nm CMOS technology, the prototype ADC achieves measured SNDR of 94.0 and 96.9 dB dynamic range (DR) in 1-kHz BW at an oversampling ratio (OSR) of 125 while only consuming $2.87~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 179.4 dB and a DR-based FoM of 182.3 dB.