The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

Ultra-low-power circuits that can work under a low-voltage supply are in great demand in future wearable biomedical applications, which tend to be integrated with low-output-voltage energy harvesting devices. In this paper, we present a low-voltage low-power continuous-time low-pass filter (CT-LPF), which is indispensable in biomedical systems. When a low-voltage supply is used, it is necessary to make the output quiescent voltage (VQ) stable in the LPF, otherwise the dynamic range will be reduced. Conventional Source-follower (SF) based topologies can achieve ultra-low-power consumption. However, the difference of the input and output VQ is sensitive to process and temperature variations. In this work, a complementary SF based topology with a bulk-common-mode-feedback (B-CMFB) circuit is proposed to keep the output VQ tracking the input VQ and immune to the process and temperature variations. A 4th-order LPF using the proposed topology has been implemented in a standard 0.18 μm CMOS process, which achieves a power consumption of only 3.69-nW under a 0.5-V voltage supply with a bandwidth of 200 Hz. Measurement results show that the input-referred noise is 91.9 μVrms. The IIP3 is 5.0 dBm and the dynamic range (DR) is 48.5 dB. The active chip area is only 0.074 mm². The proposed LPF achieves both ultra-low power consumption with a 0.5-V supply and a stable output VQ immune to process and temperature variations, which is suitable for low-supply-voltage biomedical systems.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $\Delta \Sigma \text{M}$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $\Delta \Sigma \text{M}$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $\mu \text{m}$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $\mu \text{W}$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH ² , which is more than six times better than the state of the art.

A novel all-digital phase-locked loop (ADPLL) for fast and high-linear FMCW signal generation is presented in this paper. Fast chirp slope is enabled by two-point modulation (TPM) technique and ramp linearity distortion induced by digitally- controlled oscillator (DCO) is suppressed by wide loop bandwidth. A calibration-free retiming fractional frequency dividing (FFD) scheme based on digital phase interpolator (DPI) is proposed to suppress the Δ Σ quantization noise and break the loop bandwidth limitation. A parasitic insensitive DPI is utilized in the retiming FFD scheme to achieve high-linear phase interpolation. A high frequency resolution DCO with 9.8-kHz/bit least significant bit (LSB) and a vernier time-to-digital convertor (TDC) with 2.3-ps time resolution are employed to further minimize the quantization noise. Implemented in 40-nm CMOS, the ADPLL prototype consumes 33.8 mW power and 0.32 mm² chip area. Measurement results show that 78 MHz/μs maximum chirp slope is achieved with 167 kHz root-mean-square (RMS) frequency error. The minimum RMS frequency error is only 5.6 kHz when 300 MHz frequency is swept in 1 ms. The phase noise from 12.15 GHz carrier is -113.6 dBc/Hz at 1-MHz offset.

This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the maximum detectable power. Two auxiliary capacitors in the rectifier are introduced to improve linearity at high input power dramatically. The PD with 0.4–5-GHz operating frequency can be fully integrated and has stable and reliable performance according to multiple tests. Measurement results show that the maximum detectable power achieves +35 dBm and dynamic range reaches 45 dB with ±1-dB linearity error. The proposed PD is implemented in a standard 180-nm CMOS process with 0.085 mm ² core area. The total static power consumption is 0.78 mW with a 3.3-V supply voltage.