In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 $fA/\sqrt{Hz}$ at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

This paper presents a fully integrated passive self-jamming cancellation (SJC) circuit in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology for ultra-high frequency (UHF) radio frequency identification (RFID) applications. Based on the active amplitude and phase control, a novel passive variable capacitor array and signal combiner are adopted instead of a traditional variable amplifier/attenuator and a phase shifter to reduce the circuit complexity and thus achieve higher linearity and low noise. We use an improved cancellation algorithm based on the local search method to quickly and accurately find the cancellation point that minimizes the self-jamming signal power. The simulation and measurement results are constant, and a suppression of 38 dB can be achieved in the working frequency of 860–960 MHz. The cancellation algorithm can be finished within 0.5 ms. These results indicate that the designed SJC circuit can be a promising candidate for UHF RFID applications.