This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and the quantization step of TDC is always tracked with the RO period; hence no calibration is needed in this architecture. We adopt RO tuning to lower the injection-locking bandwidth so as to decrease the power consumption of the injection current. Moreover, the fractional part of phase error detection is turned down in the coarse tuning of ADPLL to save power. An LC-based digital-controlled oscillator (LCDCO) with a 6.4 nH inductor and a resistive bias is used to have a low power and better phase noise performance. The ADPLL is fabricated in 40 nm CMOS with a 1 V supply and consumes 1.4 mW when it is locked. The measured phase noise is −114 dBc/Hz at 1 MHz offset. The test results show significant power saving. Thus, it can be a promising candidate for BLE applications.

In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 $fA/\sqrt{Hz}$ at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

This article proposes a second-order switch-capacitor filter that integrates low-pass, high-pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter through clock rate and capacitance ratio. The final filter design consists of two completely independent second-order switch-capacitor filter channels, and a 4-order Butterworth low-pass filter is designed through two-stage cascades. The two completely independent second-order switch-capacitor filters are integrated on a single chip and manufactured using the Huahong BCD350GE high-voltage 24 V process. The measurement results indicate that the proposed switch-capacitor filter achieves various functional filtering characteristics and achieves a bandwidth of 5 Hz to 10 kHz. The chip area is 5.1 × 3.1 mm${}^2$, powered by a dual power supply of ± 5 V, and the power consumption is 80 mW.

A balise is a specialized device utilized for train communication and control. However, existing balises are composed of separate components, resulting in high production costs, low integration, and significant room for improvement in stability. We propose an integrated solution, to enhance the integration of balises, reducing the number of discrete components. Additionally, we propose a feedback-enabled energy extraction circuit with a limiter-based startup circuit, to enhance the stability of the balise system. The prototype was fabricated using 180 nm high voltage(HV) complementary metal oxide semiconductor(CMOS) technology. Once implemented in the balise, the number of discrete components in the system is reduced by 25%, and the system can start up within 20 ms and operate stably. The mean data rate (MDR) deviation of the balise is only 62 ppm, which is 69% lower than that specified in the test specification for the Eurobalise form–fit–function interface specification (FFFIS), and the maximum time interval error (MTIE) is less than 250 ns.

To address the limited detection accuracy, narrow operating bandwidth, and complex structure of the charge readout circuits for photodiode arrays in an X-ray imaging system, a multi-channel charge-sensitive readout interface (ROIC) is proposed. By employing switched-capacitor circuits together with digital clock control technology, the ROIC samples the injected charges from 32 photodiodes and transfers them to a single voltage output sequentially. This design realizes multi-channel acquisition and single-channel output. The wide input range is achieved by tuning the gain of the charge-sensitive amplifier. This is accomplished by adjusting the integration feedback capacitor, which ranges from 0.5pF to 32pF. Meanwhile, to extend the gain-bandwidth product (GBW) of the core amplifier, the conventional Miller-capacitor compensation technique is replaced by three separate compensation capacitors, which further improves the overall stability. Simulation results show that the open-loop gain of the CSA amplifier is above 124dB. The GBW is larger than 2.6MHz. The channel non-linearity is 0.1% and the maximum gain error is 0.45%. Measurement results demonstrate the feasibility of the chip. The detector injunction capacitance can reach up to 60pF. It can drive a maximum load of 200pF. The chip power consumption is 43mW with a 5V supply.