Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive integrators have drawn increasing attention owing to their simplicity and power efficiency. However, a capacitor array with a passive integrator result in a huge number of unit capacitors and power consumption. This paper presents a second-order fully passive NS-SAR ADC with a segmented capacitor array and a hybrid switching procedure. We use a most-significant-bit(MSB) sampling-segmented capacitor array to reduce the number of unit capacitors, and a common mode voltage(VCM)-based hybrid switching procedure to reduce the average switching power. Compared to fully passive NS-SAR ADCs with conventional capacitor array and switching procedure, the total number of unit capacitors is reduced by about 84%, and the average switching power is also reduced by about 97.8%. The prototype was fabricated using 180nm complementary metal oxide semiconductor(CMOS) technology, it only uses 478 unit capacitors, resulting in an area of 0.086 mm ² . It consumes 16.5 μW, achieves 73.7 dB peak signal-to-noise-and-distortion ratio(SNDR), and a Schreier figure of merit(FoMs) of 165.5 dB.

This article presents a wide-range and high-precision analog front-end circuit for multi-parameter sensors that can handle sensor outputs of different types (R, C, V). A rail-to-rail baseline compensation method has been proposed, which further incorporates a fine offset elimination of 0.6 mV/step. Additionally, self-zeroing and correlated double-sampling techniques are integrated to reduce low-frequency noise and offset, prevent sensor signal saturation, and enhance the precision of the analog front-end circuit. By incorporating variable components in the sensor signal acquisition circuit and integrating them with the baseline compensation circuit, the applicability range of the sensor has been expanded (R: 7 $\mathsf{\Omega }$–1.7 M$\mathsf{\Omega }$, C: 50 fF–35 pF, V: 0.05–1.7 V). Test results show all interface circuits exhibit significant total conversion gains (C: 45 mV/fF, R: 14.5 mV/$\mathsf{\Omega }$, V: 144 V/V), achieving high precision. Meanwhile, a coefficient of determination ($R^2$) greater than 0.998 indicates high conversion linearity of the circuit.

In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 $fA/\sqrt{Hz}$ at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

A balise is a specialized device utilized for train communication and control. However, existing balises are composed of separate components, resulting in high production costs, low integration, and significant room for improvement in stability. We propose an integrated solution, to enhance the integration of balises, reducing the number of discrete components. Additionally, we propose a feedback-enabled energy extraction circuit with a limiter-based startup circuit, to enhance the stability of the balise system. The prototype was fabricated using 180 nm high voltage(HV) complementary metal oxide semiconductor(CMOS) technology. Once implemented in the balise, the number of discrete components in the system is reduced by 25%, and the system can start up within 20 ms and operate stably. The mean data rate (MDR) deviation of the balise is only 62 ppm, which is 69% lower than that specified in the test specification for the Eurobalise form–fit–function interface specification (FFFIS), and the maximum time interval error (MTIE) is less than 250 ns.

This paper presents a fully integrated passive self-jamming cancellation (SJC) circuit in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology for ultra-high frequency (UHF) radio frequency identification (RFID) applications. Based on the active amplitude and phase control, a novel passive variable capacitor array and signal combiner are adopted instead of a traditional variable amplifier/attenuator and a phase shifter to reduce the circuit complexity and thus achieve higher linearity and low noise. We use an improved cancellation algorithm based on the local search method to quickly and accurately find the cancellation point that minimizes the self-jamming signal power. The simulation and measurement results are constant, and a suppression of 38 dB can be achieved in the working frequency of 860–960 MHz. The cancellation algorithm can be finished within 0.5 ms. These results indicate that the designed SJC circuit can be a promising candidate for UHF RFID applications.