A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for 2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer and 6-bit binary coding are adopted, utilizing switching-order shuffling in combination with dynamic element matching (DEM) to suppress the spurious tones owing to the current-source mismatch in three-dimensional FinFETs. In addition, output switches are designed to achieve make-before-break operation with the proposed low crossing point level shifter. Moreover, an output full-scale current trimming method is applied to maximize the power efficiency of the envelope-tracking (ET). The active area of a single DAC is 0.036 mm², its power consumption is 6.1 mW, and its SFDR is 80 dBc.

This paper proposes a continuous-rate referenceless clock and data recovery (CDR) circuit operating in the half-rate clocking mode with a jitter-tolerant frequency acquisition technique. The proposed coarse frequency detector reduces frequency error below 40,000 ppm without any sub-harmonic lock even when the input jitter presents up to 0.6 UI _pp . The deadzone-compensated frequency detector further reduces the residual frequency error below 1,000 ppm for the following PLL's reliable operation. The CDR fabricated in a 28-nm CMOS process shows a wide capture range of 4.0 Gb/s to 10.0 Gb/s with a bit error rate (BER) under 10 ^-12 .

A referenceless digital clock and data recovery (D-CDR) circuit using a half-rate jitter-tolerant frequency detector (FD) and a multi-bit decimator is presented. For a referenceless configuration, we introduced a half-rate jitter-tolerant digital quadricorrelator frequency detector (JT-DQFD). Additionally, we proposed a multi-bit decimator circuit that losslessly down-samples up/down data from a phase detector to reduce the recovered clock jitter. The down-sampled multi-bit phase information is processed by a digital loop filter to adjust the phase of the recovered clock. Fabricated in a 28-nm CMOS technology, the test chip achieves a power efficiency of 1.3 pJ/bit at 10 Gb/s.