This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10 ^-12 over a wide temperature range from -20 °C to 120 °C.

This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20 $\Omega$ is used as a transmitter (TX) impedance instead of 50 $\Omega$ . To maximize eye openings further, fractionally spaced feedforward equalization (FS-FFE) is used with a tap spacing of 0.8 UI. The relaxed termination scheme along with FS-FFE improves eye openings by 2.25 times compared with the conventional design using a 50- $\Omega$ TX impedance with 1-UI spacing FFE.

This paper proposes a continuous-rate referenceless clock and data recovery (CDR) circuit operating in the half-rate clocking mode with a jitter-tolerant frequency acquisition technique. The proposed coarse frequency detector reduces frequency error below 40,000 ppm without any sub-harmonic lock even when the input jitter presents up to 0.6 UI _pp . The deadzone-compensated frequency detector further reduces the residual frequency error below 1,000 ppm for the following PLL's reliable operation. The CDR fabricated in a 28-nm CMOS process shows a wide capture range of 4.0 Gb/s to 10.0 Gb/s with a bit error rate (BER) under 10 ^-12 .

This paper describes a voltage-mode transmitter that supports both non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) signal transmission. A 2-tap feed-forward equalizer (FFE) is implemented with PAM4 equalization logic consisting of three stages of logic gates and two separated voltage-mode drivers for multi-level generation. Equalization is performed in both the NRZ and PAM4 signal transmission modes. A prototype chip is fabricated using a 28-nm CMOS process. When transmitting 500-mVp-p signals using the proposed transmitter, 41.13 mW power is consumed from a 1-V power supply during the 32-Gb/s PAM4 transmission.

A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (CTLE) on the receiver (RX) side compensates for the channel attenuation. Based on the maximum eye algorithm, the peaking gain of CTLE is adaptively controlled to track a time-variant environment, such as PVT variations. Each TX and RX is implemented with clocking circuits: a differential PLL, and a dual-loop clock and data recovery circuit. The proposed transceiver is fabricated in a 45-nm CMOS process, and the entire TX and RX, respectively, consume 92 and 138 mW under a 1.2-V supply while operating at 12.5 Gb/s.

This letter presents a 20 Gb/s/pin single-ended PAM-4 transceiver implemented in an 8nm CMOS process, featuring an advanced switching jitter compensation (SWJC) technique and a DQS-driven amplifier bias generation method for a source-synchronous clocking system, aimed for next-generation low-power memory interfaces utilizing multi-level signaling. The proposed pre-channel SWJC (pre-SWJC) in the transmitter adjusts the input edge timing of the thermometer PAM-4 driver to control the transitions of the PAM-4 signal. This transition control advances the outermost transitions, thereby not only minimizing the switching jitter (SWJ) of the middle eye but also enhancing the effectiveness of the post-channel SWJC (post-SWJC) performed at the receiver. Ultimately, the comprehensive solution combining the proposed pre/post-SWJC improved the timing margin from 0.26 UI to 0.39 UI at a BER of 1e-12, with only a 4.5% increase in power consumption and a 0.59% area overhead. Additionally, the proposed DQS-driven biasing technique in the receiver supplies biases for the amplifiers in the data lanes by utilizing the common-mode feedback of the replica amplifier in the differential clock lane. This approach reduces variation sources compared to the self-biasing structure that uses common-mode feedback in the data lanes, thereby improving the standard deviation of the amplifier’s bias voltage and gain variation by 58.3%.