Jose Monteiro

Prof. Jose Monteiro

Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento, Lisbon, Lisboa, Portugal
+1
orcid

Research Focus & Metrics

Academic Career Length

33Years (1994-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 December 1994 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
MAM. Alidina
M. Alidina
JMJose Monteiro
Jose Monteiro
SDS. Devadas
S. Devadas
AGA. Ghosh
A. Ghosh
MPM. Papaefthymiou
M. Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.

4 March 2022 in Remote Sensing
Verified
Journal Article
Open access
PDF file
HCHelena Cruz
Helena Cruz
Mário VéstiasMário Véstias
Mário Véstias
JMJose Monteiro
Jose Monteiro
HNHorácio Neto
Horácio Neto
Rui Policarpo DuarteRui Policarpo Duarte
Rui Policarpo Duarte
Designing synthetic-aperture radar image formation systems can be challenging due to the numerous options of algorithms and devices that can be used. There are many SAR image formation algorithms, such as backprojection, matched-filter, polar format, Range–Doppler and chirp scaling algorithms. Each algorithm presents its own advantages and disadvantages considering efficiency and image quality; thus, we aim to introduce some of the most common SAR image formation algorithms and compare them based on these two aspects. Depending on the requisites of each individual system and implementation, there are many device options to choose from, for instance, FPGAs, GPUs, CPUs, many-core CPUs, and microcontrollers. We present a review of the state of the art of SAR imaging systems implementations. We also compare such implementations in terms of power consumption, execution time, and image quality for the different algorithms used.

20 May 2008 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
LALevent Aksoy
Levent Aksoy
ECEduardo da Costa
Eduardo da Costa
Paulo FloresPaulo Flores
Paulo Flores
JMJose Monteiro
Jose Monteiro
The main contribution of this paper is an exact common subexpression elimination algorithm for the optimum sharing of partial terms in multiple constant multiplications (MCMs). We model this problem as a Boolean network that covers all possible partial terms that may be used to generate the set of coefficients in the MCM instance. We cast this problem into a 0-1 integer linear programming (ILP) by requiring that the single output of this network is asserted while minimizing the number of gates representing operations in the MCM implementation that evaluate to one. A satisfiability (SAT)-based 0-1 ILP solver is used to obtain the exact solution. We argue that for many real problems, the size of the problem is within the capabilities of current SAT solvers. Because performance is often a primary design parameter, we describe how this algorithm can be modified to target the minimum area solution under a user-specified delay constraint. Additionally, we propose an approximate algorithm based on the exact approach with extremely competitive results. We have applied these algorithms on the design of digital filters and present a comprehensive set of results that evaluate ours and existing approximation schemes against exact solutions under different number representations and using different SAT solvers.

1 September 1995 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
CTChi-Ying Tsui
Chi-Ying Tsui
JMJose Monteiro
Jose Monteiro
MPMassoud Pedram
Massoud Pedram
SDSrinivas Devadas
Srinivas Devadas
ADA.M. Despain
A.M. Despain
BLBinshan Lin
Binshan Lin
Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies.

30 December 2002
Verified
Conference Paper
Closed access
JMJose Monteiro
Jose Monteiro
SDS. Devadas
S. Devadas
AGA. Ghosh
A. Ghosh

5 April 2023 in ACM Transactions on Sensor Networks
Verified
Journal Article
Open access
LOLeonardo L. de Oliveira
Leonardo L. de Oliveira
GEGabriel H. Eisenkraemer
Gabriel H. Eisenkraemer
ECEverton A. Carara
Everton A. Carara
JMJoão B. Martins
João B. Martins
JMJose Monteiro
Jose Monteiro
This article provides a comprehensive survey of pioneer and state-of-the-art localization algorithms based on the mobility of the network. The basic concepts of the localization task in a wireless sensor network are revisited and the most common techniques suitable for random mobility are reviewed. This survey compiles and discusses the most relevant algorithms regarding localization in mobile networks, focusing on scenarios where nodes have no control over their mobility and hardware restrictions are imposed, including recent advances in learning-based solutions. It focuses on presenting techniques that do not rely on human intervention or a specialized field configuration. This unpredictability brings challenges that are not present in a static network nor in a mobile network built upon robotic entities. The basis for theoretical concepts of localization algorithms is gathered and organized in a comprehensive way, so researchers may quickly get started in this field. Significant aspects addressed throughout the article, such as mobility pattern, range scheme, and computational complexity are organized and discussed as well as performance data for quantitative analysis alongside related ponderations. This survey concludes by pointing out current and future trends.