In this paper, the impact of negative bias temperature instabilities (NBTIs) on commercial power p-channel Vertical Double-Diffused MOS (VDMOS) transistors from the standpoint of practical applications was analyzed. The effects of NBTI are one of the main reliability concerns for this type of device, so it is necessary to investigate how these effects influence various applications. A series of experiments were carried out including negative bias temperature stressing, infra-red thermographic recording and circuit characterization, with the goal of evaluating the effects of negative bias temperature stressing on the self-heating of samples in load-driving circuits operating with higher currents and circuit performance of a CMOS inverter circuit containing the examined samples. The findings suggest that negative bias temperature stressing-induced threshold voltage shift directly affects increased self-heating in load-driving circuits and that it also directly affects transfer and dynamics characteristics in CMOS inverters.

This work focuses on analyzing the influence of thermal relaxation following prolonged NBTS (Negative Bias Temperature Stress). The experimental setup features a CMOS inverter composed of a p-channel IRF9520 and a n-channel IRF510 transistor, with dynamic characteristics evaluated over a wide temperature range from −40°C to +180 °C. Comparison between the characteristics of a CMOS inverter consisting of a non-stressed and stressed PMOS devices is given. PMOS samples were divided into three groups. All of the groups were subjected to the NBT stressing, after which the first group was subjected to thermal relaxation at 175°C, the second one at 25°C and the third one at −25°C. Threshold voltage value was monitored during the NBT stress and thermal relaxation. The results demonstrate a clear correlation between temperature, threshold voltage shifts, and CMOS inverter switching times. The highest thermal relaxation temperature (175°C) partially mitigates the NBTS induced PMOS threshold voltage shift, leading to faster inverter response. This study emphasizes the importance of accounting for both aging and recovery phenomena when analyzing the dynamic performance of CMOS circuits, especially in applications exposed to elevated or negative temperatures and extended operation.

This study investigates the effects of NBTI on p-channel Vertical Double-Diffused MOSFETs (VDMOS), focusing on threshold voltage degradation and the potential for recovery through thermal relaxation. Devices were subjected to static NBT stress followed by relaxation at various temperatures. The measured transfer characteristics revealed a shift along the voltage axis, indicating changes in threshold voltage during the early stress phases, followed by saturation over time. High-temperature relaxation induced partial recovery of the degraded parameters, while low-temperature treatments had no significant recovery effect. These findings contribute to a better understanding of degradation and recovery mechanisms in power VDMOS transistors and support the design of more reliable, high-performance electronic systems.

This study investigates the self-heating effect (SHE) in p-channel VDMOS transistors under dynamic stress conditions. SHE was measured on IRF9520 devices in fresh samples, as well as after negative bias temperature (NBT) stress and subsequent relaxation treatments. Thermal analysis was conducted using pulsed gate signals with a 50% duty cycle and rise/fall times of 5 ns, 100 ms, and 250 ms, at fixed drain current levels of 0.5 A, 1 A, 1.5 A, and 2 A to assess temperature variations in both fresh devices and components previously subjected to NBT stress and thermal relaxation. The goal was to investigate the operating conditions of the component when they are integrated into an actual electronic system.

This paper presents an experimental and SPICE-based modeling approach for analyzing NBTI (Negative Bias Temperature Instability) and SHE (Self-Heating Effects) in power p-channel VDMOS transistors IRF9520. The objective is to enhance existing models and enable accurate prediction of device behavior under prolonged electrical and thermal stress, as well as during the recovery (relaxation) phase. Experiments were performed by applying a gate stress of - 45 V at $175\,{}^{\circ}\mathrm{C}$ for 96 hours, followed by relaxation at multiple temperatures ranging from $-40\,{}^{\circ}\mathrm{C}$ to $175\,{}^{\circ}\mathrm{C}$, based on which the degradation models were developed. Voltage shift data were fitted using power-law and exponential-law expressions, and implemented in SPICE for long-term performance estimation. Additionally, self-heating effects were characterized using thermal imaging under different signal shapes and current levels, and modeled using equivalent RC networks. The proposed models show good agreement with experimental data and can be used to predict degradation trends in power PMOS transistors for reliability-aware circuit design.