This paper studies negative bias temperature instability in commercial IRF9520 p-channel power VDMOSFETs under both static and pulsed bias stress conditions in order to model this effect. The pulsed voltage stressing caused generally lower shifts as compared to static stressing performed at the same temperature with equal stress voltage magnitude, as a consequence of partial recovery during the low level of pulsed gate voltage. It was shown that the quantitative differences between static and pulsed NBT stress depend on the duty cycle, and the differences become more significant as the duty cycle decreases. It was found that 25 off-time of the pulsed stress voltage could suffice to remove the major part of the recoverable component of the degradation created during the foregoing pulse on-time. An equivalent electrical circuit has been proposed and on the basis of these experimental results a modeling of threshold voltage shifts induced by pulsed negative bias temperature stress has been done.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

We report on a procedure for extracting the SPICE model parameters of a RADFET sensor with a dielectric HfO₂/SiO₂ double-layer. RADFETs, traditionally fabricated as PMOS transistors with SiO₂, are enhanced by incorporating high-k dielectric materials such as HfO₂ to reduce oxide thickness in modern radiation sensors. The fabrication steps of the sensor are outlined, and model parameters, including the threshold voltage and transconductance, are extracted based on experimental data. Experimental setups for measuring electrical characteristics and irradiation are described, and a method for determining model parameters dependent on the accumulated dose is provided. A SPICE model card is proposed, including parameters for two dielectric thicknesses: (30/10) nm and (40/5) nm. The sensitivities of the sensors are 1.685 mV/Gy and 0.78 mV/Gy, respectively. The model is calibrated for doses up to 20 Gy, and good agreement between experimental and simulation results validates the proposed model.

This paper gives insight on the WebSocket communication method in Internet of Things system, where the hardware part of the system is based on ESP32 microcontroller. Method of implementation is discussed and the reliability of the real-time data transfer in Wi-Fi networks is tested and compared with the long-polling method. Special circuit is designed with the goal to stress the hardware part of the system and the client-server communication link in order to enable proper comparison of data transfer methods. For the comprehensive testing of the real-time data ow, a web server application is designed and used to visualize received data. Impact of RSSI on transfer methods is discussed as well. Eciency of the WebSocket method is discussed and then compared to the long-polling method.

This study examines the effects of negative bias temperature (NBT) stress on irradiated commercial p-channel power VDMOS transistors, with a focus on contribution to threshold voltage shift of changes in gate oxide charge and interface traps. The research addresses the critical reliability concerns for these transistors, as shifts in the threshold voltage can notably influence device performance, particularly under conditions of elevated temperature and negative gate oxide fields. Considering that VDMOS transistors are power devices, high temperatures occur during their operation, which can cause NBT effects, and this definitely affects normal operation. Furthermore, the study investigates the implications of irradiation on the electrical parameters of VDMOS power transistors, highlighting the need for a thorough understanding of these effects. The experimental methodology includes both irradiation and subsequent NBT stress application. This paper provides a detailed analysis of both static and pulsed NBT stressing, with an emphasis on novel stress signals related to practical applications. The data presented in the paper were obtained by exposing components to NBT stresses with different polarizations on the gate, which were previously exposed to radiation to different doses, with and without polarization. Also, the results with different frequencies applied during NBT stress are presented. Results from the study elucidate the roles of gate oxide charge and interface traps in contributing to threshold voltage shifts, thereby offering critical insights into the reliability of p-channel power VDMOS transistors in various operational stress scenarios. Self-heating during both the operational and cooling phases of fresh and previously irradiated components were measured using IR camera These findings are instrumental for the design and operation of electronic systems that utilize these transistors, ensuring improved reliability and performance.

This paper gives insight in reliability of p-channel VDMOSFET power transistors subjected to NBT stressing. Effects that lead to degradation of characteristics of these electronic circuits are presented, out of which threshold voltage shift with NBT stressing is further analysed. Measurements have been done and experimental results of the threshold voltage degradation of power transistors IRF9520 caused by different types of negative bias temperature stressing are shown. Stressing types, both static and pulsed, and their impact on transistors, especially on threshold voltage shifts have been explained in more details. An elementary equivalent electrical circuit is designed and proposed with the goal to model impact of both types of stressing, and also to calculate and estimate reliability of the circuit under specified stress. All of the elements of the modeling circuit and their dependencies are explained. Example of modeling from the experimental data is given together with the comparison between measured and modeled results. Differences between obtained results are discussed.