This brief presents the design of a 120 GHz $g_{m}$ -boosting low-noise amplifier (LNA) in 40-nm CMOS. The proposed LNA consists of a single-stage differential $g_{m}$ -boosting common-gate (CG) amplifier and a four-stage differential capacitance-neutralized common-source amplifier. A triple-coupled transformer-based $g_{m}$ -booting technique in the CG stage enhances gain and noise figure (NF) performances. Implemented in 40 nm CMOS, the proposed LNA achieves a measured power gain of 23.8 dB at 123 GHz with a 3-dB bandwidth of 10 GHz. The lowest NF is 5.0 dB at 123 GHz and the NF is below 6.5 dB from 114 to 128 GHz. The LNA consumes 26 mW from a 1-V supply, with a core chip area of 0.25 mm $\times 0$ .70 mm.

In this paper, we present a 6-stage 120 GHz hybrid low noise amplifier (LNA) for sub-THz radar systems. To enhance the noise figure (NF) and gain performance of the LNA, we propose a hybrid architecture that utilizes a combination of 2-stage single-ended and 4-stage differential common-source amplifiers. The first 2-stage single-ended common-source amplifier provides low-loss and low-noise characteristics, while the 4-stage differential common-source amplifier provides high gain, resulting in low noise and high gain performance. Implemented in a 40 nm CMOS process, the LNA occupies a chip area of 0.099 mm ² excluding the pads. The measurement results show that the proposed LNA achieves a low NF of 5.5 dB, a high gain of 27.5 dB, and an input 1-dB compression point of -29.5 dBm at 122.5 GHz with a power consumption of 27.4 mW.

In this paper, we present a millimeter-wave CMOS down-conversion mixer designed for 5G cellular communications. The proposed mixer integrates a local oscillator buffer, an RF transconductance (Gm) stage, and a switching stage. A transformer-based harmonic suppression technique and separate RF Gm stage and switching stage are employed to achieve a low noise figure (NF), high conversion gain (CG), and effective harmonic suppression. Intermodulation and gain characteristics are analyzed, demonstrating enhanced harmonic suppression, high gain, and low NF. Implemented in 65 nm CMOS technology, the proposed mixer occupies a core chip area of 0.51 mm² and consumes a dc power of 7 mW. The implemented design achieves a CG of 6.4 dB, an NF of 6.1 dB, and an output third-order intercept point of 9.0 dBm at an RF frequency of 38.2 GHz. Additionally, harmonic suppression exceeds −26 dBc, highlighting the performance advantages of the proposed architecture.

In this article, we present a 60 GHz low-phase-error current-reuse variable-gain amplifier (VGA) in 65 nm CMOS. The proposed VGA consists of an input stage, a variable gain stage, and an output stage. An impedance-invariant VGA is used to reduce phase error during gain control. Furthermore, a transformer-based current-reuse technique is adopted to reduce dc power consumption and enhance the gain. Implemented in 65 nm CMOS technology, the proposed VGA occupies a chip area of 0.38 mm², including pads, and consumes a dc power of 15 mW. The implemented design achieves a gain of 13.2 dB, a gain control range of 20 dB, and an RMS phase error less than 2.65° over 50–67 GHz. Additionally, the input 1-dB compression point is −11 dBm at 60 GHz.