A Trench-gate Field Stop Insulated Gate Bipolar Transistor (TFS-IGBT) with a novel hybrid p+/n collector structure is proposed to enhance the trade-off relationship between the on-state voltage drop (Von) and the turn-off energy loss (Eoff). The proposed hybrid collector structure consists of a p+/n layer between the p+ collector and the Field Stop layer. During turn-on, the p+ regions in the hybrid p+/n layer provide high carrier injection efficiency. During turn-off transient, the n-regions in the hybrid p+/n collector provide fast carrier extraction paths for holes. Two-dimensional numerical simulations comparing a Conventional TFS-IGBT, an Injection Efficiency Controlled IGBT with the proposed Hybrid p+/n Collector TFS-IGBT (HC-IGBT) having similar device structures show that for a 1.2 kV rating and with Von at 1.5 V, the HC-IGBT has an advantage in Eoff reduction by 69% and 22%, respectively. Finally, backside mask alignment is not needed for fabricating the proposed hybrid p+/n collector structure.

MOS current mode logic is a kind of differential symmetric logic circuits. Its power consumption is relatively low at high frequency compared to traditional CMOS logic, and it has typical high speed and low power character. In this paper, MOS current mode logic circuits with different input terminal were analyzed; two circuit structures were proposed to realize MOS current mode logic full adder and the application were given for different circuit structure.

A novel heat dissipation structure composed of square frustums thermal through silicon via array and embedded in P-type (100) silicon substrate is proposed to improve the heat dissipation capacity of power chips while reducing process difficulty. Based on theoretical analysis, the heat transfer model and thermo-electric coupling reliability model of a power chip with the proposed heat dissipation structure are established. A comparative study of simulation indicates that the proposed heat dissipation structure, which can avoid problems such as softness, poor rigidity, fragility and easy fracture caused by thinning chips has better heat dissipation capability than thinning the substrate of power chips.

In this work, we have developed a novel method for simultaneously performing interlayer copper interconnecting and Cu filling inside TSVs. It was applied to demonstrate two-layer stacked chips that process the development of interlayer copper interconnecting and Cu pillar filling in through-silicon vias (TSVs) by copper electroplating at room temperature (25 °C). In the two-layer stacked structure, a chip with TSVs was bonded with another chip without TSVs using a permanent bonding adhesive. After all micro-channels were immersed in the copper sulfate electroplating solution by vacuum pumping, copper electroplating made the interlayer copper interconnecting structures and the simultaneously filled copper pillars in TSVs a homogeneous three-dimensional (3D) interconnected structure and did not show original interfaces. Furthermore, no apparent gaps, air bubbles, or cracks were observed in the 3D copper interconnecting structure. The measured direct current resistance and the critical frequency at which the skin effect occurs of the formed 3D copper interconnected structure were very close to the theoretical value. The pure copper 3D interconnected structure without inner interfaces is very valuable for high-quality 3D integrated systems.

Three-dimensional (3D) integration based on through silicon via (TSV) is one of the most promising technologies in the post-Moore Era. However, increased power density will cause great challenge in heat dissipation and affect the reliability of 3D integrated systems, especially 3D power integrated systems. Except for signal connections, TSV can also be used as thermal conduction pathway. An embedded heat dissipation structure with different size TSVs in different layers of power chips is proposed in this paper. The radius of TSVs in the lower dies is larger than that in the upper dies. Numerical investigation indicates that, compared with the embedded heat dissipation structure with uniform TSV, the proposed structure with the radius of TSVs from top to bottom is 11 μm, 20 μm, and 23 μm, can significantly improve the cooling capability. The volume of heat sink of the proposed structure is much smaller than that of two-dimensional structure. Increasing the number of internal fins has improved heat dissipation effect for the proposed structure.