Focusing on the interplay between interface chemistry, electrochemistry, and integrated electronics, we show a novel low-cost and flexible biosensing platform for continuous glucose monitoring. The amperometric biosensing system features a planar three-electrode structure on a plastic substrate, and a wireless NFC-powered electronic system performing sensor analog front-end (AFE), A/D conversion, digital control, and display tasks. The working electrode is made of electropolymerized poly(3,4-ethylenedioxythiophene) (PEDOT) film onto an Au/PET electrode followed by immobilization of cross-linked glucose oxidase by glutaraldehyde. The advantages offered by such a device, including low-cost materials and instrumentation as well as the good sensitivity of 9.24 μA/(mM · cm2) are promising tools for point-of-care monitoring. It is demonstrated that the devices are good candidates for the development of advanced sensing approaches based on the investigation of the noise produced during operation (Fluctuation Enhanced Sensing).

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectric–semiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel–Kramers–Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at $\sim 100$ nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.

We investigated the capacitance of a forward-biased silicon pn diode using impedance spectroscopy. Despite extensive research spanning decades, no single model in the literature adequately describes the impedance behavior for bias up to the built-in voltage. By employing the 1N4007 diode as a case study, we analyzed the impedance over a wide frequency range, from 1 Hz to 1 MHz. Our analysis reveals that impedance can be effectively studied by combining two models. In both models, the depletion capacitance is assumed to be an ideal capacitor with a value independent of frequency. One model accounts for diffusion processes, while the other addresses interfacial effects, as well as potential and capacitance distributions across the junction. This approach offers valuable insights into the complex capacitance behavior of pn junctions as a function of the bias voltage. Measurements of depletion and diffusion capacitances, as well as of the diode transit time can be achieved from a set of impedance spectroscopy data.

We propose an open loop voltage amplifier topology based on a single JFET front-end for the realization of very low noise voltage amplifiers to be used in the field of low frequency noise measurements. With respect to amplifiers based on differential input stages, a single transistor stage has, among others, the advantage of a lower background noise. Unfortunately, an open loop approach, while simplifying the realization, has the disadvantage that because of the dispersions in the characteristics of the active device, it cannot ensure that a well-defined gain be obtained by design. To address this issue, we propose to add two simple operational amplifier-based auxiliary amplifiers with known gain as part of the measurement chain and employ cross correlation for the calibration of the gain of the main amplifier. With proper data elaboration, gain calibration and actual measurements can be carried out at the same time. By using the approach we propose, we have been able to design a low noise amplifier relying on a simplified hardware and with background noise as low as 6 nV/√Hz at 200 mHz, 1.7 nV/√Hz at 1 Hz, 0.7 nV/√Hz at 10 Hz, and less than 0.6 nV/√Hz at frequencies above 100 Hz.

In this article we propose a method for current noise measurements which allows, at least in principle, the complete elimination of the noise introduced by the measurement amplifiers. We present a detailed circuit analysis which illustrates the advantages of the proposed measurement procedure with respect to the conventional techniques. The validity of this measurement method is confirmed by the results obtained by means of SPICE simulations and by measurements performed on a prototype circuit.