This article introduces a compact NMOS-only voltage reference that is able to operate down to a 0.25-V supply voltage and 5.4-pW power consumption. This allows reliable generation of a stable output voltage even in harvested systems under highly uncertain environmental conditions. At the system level, pW-power, 0.25–1.8-V operation, and a competitive power supply rejection ratio (PSRR) relax or eliminate the need for intermediate power conversion and supply regulation for additional power and cost reductions. The proposed voltage reference is based on a body biasing scheme assisted by replica well biasing to compensate voltage and temperature fluctuations. A 180-nm test chip shows that the proposed reference occupies an area of $2200~\mu \text{m}^{2}$ , while providing 91.4-mV output voltage with 0.51-mV (0.56%) standard deviation, $24.2~\mu \text{V}/^{\circ }\text{C}$ (265 ppm/°C) temperature coefficient, and $144.5~\mu \text{V}$ /V (0.16%/V) line sensitivity across 30 dice from the same manufacturing lot. The resulting absolute output voltage accuracy without any trimming is 2.8 mV at 3- $\sigma $ variations, 0.3-V fluctuation, and temperature change by 50 °C, improving on prior art by 1.4– $19.7\times $ . Overall, the capability of reliable operating down to ultralow voltages, pW-power, and the inherently small footprint make the proposed reference well suited for low-cost tightly constrained systems.

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-kappa gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-kappa layer closer to the Si-SiO₂ interface enhances the 1/f noise mainly due to mobility fluctuations

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of 10⁻⁶ by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions.

Smart tags are compact electronic devices affixed to or embedded into objects to facilitate identification, monitoring, and data exchange. Consequently, secure authentication of these tags is a crucial issue, as objects must reliably verify their identity before sharing sensitive information with other entities. The application of Physical Unclonable Functions (PUF) as a device's “digital fingerprint” has attracted significant attention, yet existing PUF-based authentication methods exhibit security vulnerabilities, either due to the authentication protocol itself or the limited reliability of the PUF technology used. Moreover, there has been a considerable focus on the software aspect, often overlooking the critical role of hardware design, which can become a target for attacks aimed at compromising the device's identity or act as a hindrance in the manufacturing process. In light of these points, this paper introduces an identification tag architecture that leverages PUF technology, focusing on authentication. This architecture features a straightforward but efficient authentication protocol, underpinned by a new and highly stable PUF model. The overall architecture encompasses particular hardware implementation aspects that significantly simplify the tag's enrollment phase and minimize vulnerabilities to attacks. The paper also describes a prototype of this identification tag and provide detailed insights into its application.