Single-photon sources are important for integrated photonics and quantum technologies, and can be used in quantum key distribution, quantum computing, and sensing. Color centers in the solid state are a promising candidate for the development of the next generation of single-photon sources integrated in quantum photonics devices. They are point defects in a crystal lattice that absorb and emit light at given wavelengths and can emit single photons with high efficiency. The landscape of color centers has changed abruptly in recent years, with the identification of a wider set of color centers and the emergence of new solid-state platforms for room-temperature single-photon generation. This review discusses the emerging material platforms hosting single-photon-emitting color centers, with an emphasis on their potential for the development of integrated optical circuits for quantum photonics.

Single-photon detectors have gained significant attention recently, driven by advancements in quantum information technology. Applications such as quantum key distribution, quantum cryptography, and quantum computation demand the ability to detect individual quanta of light and distinguish between single-photon states and multi-photon states, particularly when operating within waveguide systems. Although single-photon detector fabrication has been established for some time, integrating detectors with waveguides using new materials with suitable structural and electronic properties, especially at telecommunication wavelengths, creates more compact source-line-detector systems. This review explores the state of the art of single-photon detector research and examines the potential breakthroughs offered by novel low-dimensional materials in this field.

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO ₂ ) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device- and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using long-channel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver’s frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s system-level operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques.

Integrated photonics on Silicon-On-Insulator (SOI) substrates is a well developed research field that has already significantly impacted various fields, such as quantum computing, micro sensing devices, biosensing, and high-rate communications. Although quite complex circuits can be made with such technology, everything is based on a few ’building blocks’ which are then combined to form more complex circuits. This review article provides a detailed examination of the state of the art of integrated photonic building blocks focusing on passive elements, covering fundamental principles and design methodologies. Key components discussed include waveguides, fiber-to-chip couplers, edges and gratings, phase shifters, splitters and switches (including y-branch, MMI, and directional couplers), as well as subwavelength grating structures and ring resonators. Additionally, this review addresses challenges and future prospects in advancing integrated photonic circuits on SOI platforms, focusing on scalability, power efficiency, and fabrication issues. The objective of this review is to equip researchers and engineers in the field with a comprehensive understanding of the current landscape and future trajectories of integrated photonic components on SOI substrates with a 220 nm thick device layer of intrinsic silicon.

Since the 1980s, researchers have taken giant steps in understanding how to use quantum mechanics for solving real problems—for example, making a computer that works according to the laws of quantum mechanics. In recent decades, researchers have tried to develop a platform for quantum information and computation that can be integrated into digital and telecom technologies without the need of a cryogenic environment. The current status of research in the field of quantum integrated photonics will be reviewed. A review of the most common integrated photonic platforms will be given, together with the main achievements and results in the last decade.

Optical links are rapidly becoming pervasive in the readout chains of particle physics detector systems. Silicon photonics (SiPh) stands as an attractive candidate to sustain the radiation levels foreseen in the next-generation experiments, while guaranteeing, at the same time, multi-Gb/s and energy-efficient data transmission. Integrated electronic drivers are needed to enable SiPh modulators’ deployment in compact on-detector front-end modules. A current-mode logic-based driver harnessing a pseudo-differential output stage is proposed in this work to drive different types of SiPh devices by means of the same circuit topology. The proposed driver, realized in a 65 nm bulk technology and already tested to behave properly up to an 8 MGy total ionizing dose, is hybridly integrated in this work with a lumped-element Mach–Zehnder modulator (MZM) and a ring modulator (RM), both fabricated in a 130 nm silicon-on-insulator (SOI) process. Bit-error-rate (BER) performances confirm the applicability of the selected architecture to either differential and single-ended loads. A 5 Gb/s data rate, in line with the current high energy physics requirements, is achieved in the RM case, while a packaging-related performance degradation is captured in the MZM-based system, confirming the importance of interconnection modeling.