For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin–orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

We have performed micromagnetic simulations of the magnetization dynamics of the composite‐free magnetic layer in a pentalayer structure. We have found a substantial decrease of the switching time in this system as compared to the pentalayer structure of similar dimensions with a monolithic free layer. The physical reasons for the switching time reduction at the same current density are discussed.

Spin transfer torque random access memory is one of the promising candidates for future universal memory. The reduction of the current density required for switching and the increase of the switching speed are the most important challenges in this area. In this paper, a penta-layer structure with two pinned magnetic layers is studied by means of extensive micromagnetic calculations. By numerically investigating the dynamics of the switching process, a methodology of how to achieve fast and symmetric switching without a compensating magnetic field is presented. Our simulations also highlight the importance of the field acting perpendicular to the plane, which facilitates switching.

We investigate the temperature dependence of the hysteresis in the transfer characteristics of 4H silicon carbide (4H-SiC) lateral MOSFETs. Within temperatures ranging from 150 to 300 K, we experimentally characterize the hysteresis width as the difference of the threshold voltage between up and down sweeps. We observe a considerable increase in the hysteresis width toward lower temperatures. When the gate voltage sweeps up, the threshold voltage shifts toward positive gate voltages. This shift is maintained even during the subsequent down sweep. We attribute this behavior to acceptor-like border traps, which get more negatively charged at higher gate voltages. These traps are presumably located near the SiC/SiO ₂ interface with energy levels close to the SiC conduction band edge. Using a two-state non-radiative multi-phonon model, we calculated capture and emission times to show that the hysteresis width corresponds to the charge stored on these traps and, hence, possesses an intrinsic temperature dependence due to the transition barriers.

We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

Using the deterministic version of our hot-carrier degradation (HCD) model we perform a statistical analysis of the impact of random dopants (RDs) on HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.