Ru has been considered a candidate to replace Cu-based interconnects in VLSI circuits. Here, a methodology is proposed to predict the resistivity of (Ru) interconnects. First, the dependence of the Ru thin film resistivity on the film thickness is modeled by the semiclassical Mayadas-Shatzkes (MS) approach. The fitting parameters thus obtained are then used as input in a modified MS model for nanowires to calculate wire resistivities. Predicted experimental resistivities agreed within about 10%. The results further indicate that grain boundary scattering was the dominant scattering mechanism in scaled Ru interconnects.

We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

Using the deterministic version of our hot-carrier degradation (HCD) model we perform a statistical analysis of the impact of random dopants (RDs) on HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress by calculating carrier distribution functions and using a non-radiative multiphonon model. We observe charge trapping above and below the horizontal projection of the sheet in the wall. We find the charge profile not to depend on the sheet width and the trapping in the forksheet FET wall to be significantly smaller than the trapping in the gate stack.

We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form.

We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages ($V_{\mathrm{gs}}$ and $V_{\mathrm{ds}}$, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low $V_{\mathrm{gs}}$ and relatively high $V_{\mathrm{ds}}$. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages $\{V_{\mathrm{gs}},V_{\mathrm{ds}}\}$.