This article proposes transmitter coils selection method for maximum power transfer efficiency in the wireless power transfer (WPT) system with multiple transmitter coils and a single receiver coil (MTSR). The proposed method is divided into two main steps. First, transmitter coil selection criteria that can achieve maximum efficiency are derived by analyzing the relative magnitude of the coupling coefficient between each coil. Next, a method for calculating the relative coupling coefficients used for the criteria only with the input current value is presented. This method differs from previous studies in that it can be applied when some transmission coils are deactivated. Therefore, it is possible to select the optimal transmitter coil combination in consideration of the characteristics of the receiver coil using the proposed method without information on the receiver coil. By the proposed transmitter coils selection criteria, the power transfer efficiency has an average of 96.5 $\pm$ 0.5% when the output power is 300 W, even with the position change of the receiver coil. In addition, it is confirmed that the proposed coupling coefficient extraction method has a slight error of 2.5% compared to the measured value by a vector network analyzer.

Vehicular Ad-hoc Network (VANET) is an emerging technique dedicated to wireless vehicular communication to improve transportation safety by exchanging driving information between vehicles. For safety purposes, vehicles periodically broadcast a safety packet via Vehicle-to-Vehicle (V2V) communication. Accordingly, VANET safety applications demand a reliable exchange of the safety packet with high Packet Delivery Ratio (PDR), acceptable latency, and communication fairness. However, the communication performance significantly degrades due to numerous packet collisions when a large number of vehicles simultaneously access limited channel resources for the safety broadcast. In particular, the problem grows more severe in congested VANETs absent infrastructures since vehicles must control channel access using a self-adaptive scheme without external assistance. Thus, a robust and decentralized channel access protocol for VANETs is required to achieve road safety. In this paper, we propose an intelligent channel access algorithm empowered by cooperative Reinforcement Learning (RL), in which vehicles coordinate the channel access in a fully-decentralized manner. We also consider a proper interaction scheme between vehicles for enhancing the V2V safety broadcast in infrastructure-less congested VANETs. We provide evaluation results with extensive simulations according to various levels of traffic congestion. Simulations confirm the superior performance of the algorithm: the algorithm has a 20% increase in PDR compared to the latest RL-based channel access scheme. Furthermore, the algorithm satisfies the low latency requirement of VANET safety applications as well as both short-term and long-term communication fairness.

In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.

In this paper, we propose a 3D-IC PDN impedance prediction method using deep learning (DL). Unlike conventional application process (AP) and printed circuit board (PCB) design, our method proposes an effective solution to the problem of PDN design of 3D-IC, which requires accurate and fast impedance evaluation. For prediction, we construct regression neural network model based on VGG-16 with additional layers. Additionally, boundary element method (BEM) and Voronoi diagram are used to generate training data. We verified the proposed method in terms of accuracy and time. The impedance can be predicted nearly 4 times faster than ground truth which calculated by BEM with a low error.

In this paper, a fast SerDes equalizer effect-included worst eye diagram estimation method is proposed for high-speed serial links. The proposed approach analytically integrates the effects of linear and nonlinear equalizers in the frequency and time domains, respectively, based on the behavior of the equalizers. This approach enables fast single-bit response (SBR) calculations without requiring input/output buffer information specifications, i.e., an algorithmic model interface (IBIS-AMI) model-based transient simulation. Additionally, a modified peak distortion analysis (PDA)-based worst eye estimation method was employed, including the outer contours. To validate the proposed method, tests were conducted in a peripheral component interconnect express (PCIe) Gen 6.0 channel environment configured with various equalizer combinations and different loss conditions. The proposed method achieves eye contour results comparable to those in conventional circuit simulations, operating up to 255 times faster than bit-by-bit methods and up to 66 times faster than statistical methods. The proposed method offers significant advantages in environments that require rapid exploration of optimal channel and equalizer combinations, providing substantial time savings and efficient evaluations.

In this paper, a deep reinforcement learning (DRL) approach that optimizes the power/ground ball map design within the ball grid array (BGA) package of 3D-ICs considering multiple-power-domain (MPD) environments is proposed. With the adoption of MPD in 3D-ICs, the BGA in the package substrate, which routes the power and ground to the appropriate power domain and components from the board, faces design challenges such as highly complex power noise between the domains and allocations considering multiple power densities. To address this design complexity, a U-net-based DRL method is adopted, which trains an optimal policy to obtain an optimal power/ground ball map to mitigate simultaneous switching noise (SSN). The U-net enables the conservation of semantic and spatial information simultaneously, allowing the proposed method to optimize the complex ball map effectively within the BGA package for MPD. Furthermore, the proposed method shows reusability and scalability by training with variously displaced current source center (CSC) balls and various ball map sizes while maintaining the power grouping design. The optimality performance of the proposed method is verified by comparing it to conventional optimization algorithms such as random search (RS) and a genetic algorithm (GA). The proposed method outperforms RS and GA in terms of the execution time and optimality performance across various tests with different ball map sizes and CSC positions.