In this paper, we propose a method to reduce the leakage magnetic field from wireless power transfer (WPT) systems with series–series compensation topology by adjusting the phase difference between the transmitter (TX) coil current and the receiver (RX) coil current without additional shielding coils or materials. A WPT system employing the proposed method adjusts the phase difference between the TX coil current and RX coil current by tuning a resonant capacitor of the RX coil. The conditions for minimizing the leakage magnetic field are derived, and the range of the resonant capacitor of RX, considering power transfer efficiency and the leakage magnetic field, is proposed. Through simulations and experiments, it is verified that the proposed method can reduce the leakage magnetic field level without any additional materials. For that reason, the proposed method can be suitable for size-limited, weight-limited or cost-limited WPT systems.

This paper proposes a shielding sensor (SS) coil to solve the misalignment issue and the leakage magnetic field issue of the wireless power transfer (WPT) system for electric vehicles (EVs). The misalignment issue and leakage magnetic field issue must be solved because they can cause problems with power transfer efficiency reduction and electronic device malfunction. To solve these problems, the proposed SS coils are located over the Tx coil. The newly created mutual inductance between the Tx coil and the SS coil is used to detect the misalignment of the receiver in the Tx coil. In addition, the current phase of the SS coil is adjusted through impedance control of the SS coil to reduce the leakage magnetic field. The proposed SS coils were applied to the standard SAE J2954 model for the wireless charging of an EV. The WPT3/Z2 model of SAE J2954 with output power of 10 kW was simulated to compare the shielding effect according to the power transfer efficiency, and it was confirmed that a shielding effect of 76% was shown under the condition of a 3% reduction in the power transfer efficiency. In addition, the occurrence and direction of the misalignment between the receiver and the Tx coil were confirmed by using the tendency of mutual inductance between each SS coil and the Tx coil. In addition, as in the simulation result, the shielding effect and tendency were confirmed in an experiment conducted with the output power downscaled to 500 W.

In this article, we propose a method for deembedding the effects of mounting pads and via-holes in test fixture for accurate impedance measurement of the passive component of surface mount devices (SMDs). Impedance of the SMD passive component is measured mounted on the test fixture because it cannot be probed directly. Hence, the measurement results include the effects of the test fixture. Deembedding is required to extract the impedance of the device under test alone. Existing deembedding methods such as short-open-load-thru (SOLT), thru-reflect-line (TRL), and 2x thru deembedding cannot eliminate the effects of the mounting pads and via-holes of the test fixture, leading to large measurement errors. Our proposed method can extract the parasitic components of the mounting pads and via-hole using open and short fixtures, and then deembed the mounting pads and via-hole. Furthermore, two guidelines for designing the short and open fixtures are proposed. We validated our proposed method through a simulation and measurement. From the measurement result of the multilayer ceramic capacitors, the difference in the equivalent series inductance (ESL) between the 2x thru deembedding method and the proposed method was analyzed. Additionally, we confirmed that the self-impedance and SSN voltage of the power distribution network (PDN) had larger value due to the ESL error. By reducing the ESL error, the SSN voltage was decreased by about 5%, thus saving the number of decoupling capacitors.

The electromagnetic interference (EMI) and dynamic capacitance characteristics of metal-oxide-semiconductor field-effect transistors ( mosfet s) are essential considerations in circuit design and electromagnetic compatibility. A mosfet is a semiconductor widely used in switching applications. The dynamic capacitance characteristics of a mosfet are closely related to the switching behavior of the circuit and EMI generation. Therefore, for EMI analysis and to control power conversion systems, the capacitances of the mosfet s have to be accurately known. The capacitance of a mosfet changes depending on the dc bias voltage. In other words, this means that EMI characteristics may vary depending on operating conditions, so capacitance must be obtained based on the dc voltage. Much research has been conducted on the capacitance extraction of a single mosfet . However, the complexity of the half-bridge structure increases as the number of terminals increases, so conventional research has limitations. This article proposes a method to extract the half-bridge mosfet dynamic capacitances simply using a one-step measurement. By changing the terminal connection of the half-bridge mosfet , the dynamic capacitances were obtained through two-port S-parameter measurement. The proposed method was verified through simulation and experiment, and a switching test was performed for EMI analysis.

In this paper, a fast SerDes equalizer effect-included worst eye diagram estimation method is proposed for high-speed serial links. The proposed approach analytically integrates the effects of linear and nonlinear equalizers in the frequency and time domains, respectively, based on the behavior of the equalizers. This approach enables fast single-bit response (SBR) calculations without requiring input/output buffer information specifications, i.e., an algorithmic model interface (IBIS-AMI) model-based transient simulation. Additionally, a modified peak distortion analysis (PDA)-based worst eye estimation method was employed, including the outer contours. To validate the proposed method, tests were conducted in a peripheral component interconnect express (PCIe) Gen 6.0 channel environment configured with various equalizer combinations and different loss conditions. The proposed method achieves eye contour results comparable to those in conventional circuit simulations, operating up to 255 times faster than bit-by-bit methods and up to 66 times faster than statistical methods. The proposed method offers significant advantages in environments that require rapid exploration of optimal channel and equalizer combinations, providing substantial time savings and efficient evaluations.

In this paper, a deep reinforcement learning (DRL) approach that optimizes the power/ground ball map design within the ball grid array (BGA) package of 3D-ICs considering multiple-power-domain (MPD) environments is proposed. With the adoption of MPD in 3D-ICs, the BGA in the package substrate, which routes the power and ground to the appropriate power domain and components from the board, faces design challenges such as highly complex power noise between the domains and allocations considering multiple power densities. To address this design complexity, a U-net-based DRL method is adopted, which trains an optimal policy to obtain an optimal power/ground ball map to mitigate simultaneous switching noise (SSN). The U-net enables the conservation of semantic and spatial information simultaneously, allowing the proposed method to optimize the complex ball map effectively within the BGA package for MPD. Furthermore, the proposed method shows reusability and scalability by training with variously displaced current source center (CSC) balls and various ball map sizes while maintaining the power grouping design. The optimality performance of the proposed method is verified by comparing it to conventional optimization algorithms such as random search (RS) and a genetic algorithm (GA). The proposed method outperforms RS and GA in terms of the execution time and optimality performance across various tests with different ball map sizes and CSC positions.