In this paper, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate’s effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented, and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7 % and 4.7 % at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1 % at 8 Gb/s, verifying the low-power structure.

It is necessary to reduce the crosstalk noise in high-speed signaling channels. In the channel routing area, the tabbed routing pattern is used to mitigate far-end crosstalk (FEXT), and the electrical length is controlled with a time domain reflectometer (TDR) and time domain transmission (TDT). However, unlike traditional channels having uniform width and space, the width and space of tabbed routing changes by segment, and the capacitance and inductance values of tabbed routing also change. In this paper, we propose a tabbed routing equivalent circuit modeling method using the segmentation approach. The proposed model was verified using 3D EM simulation and measurement results in the frequency domain. Based on the calculated inductance and capacitance parameters, we analyzed the insertion loss, FEXT, and self-impedance in the frequency domain, and TDT and FEXT in the time domain, by comparing the values of these metrics with and without tabbed routing. Using the proposed tabbed routing model, we analyzed tabbed routing with variations of design parameters based on self- and mutual-capacitance and inductance.

In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.

In this paper, we propose a 3D-IC PDN impedance prediction method using deep learning (DL). Unlike conventional application process (AP) and printed circuit board (PCB) design, our method proposes an effective solution to the problem of PDN design of 3D-IC, which requires accurate and fast impedance evaluation. For prediction, we construct regression neural network model based on VGG-16 with additional layers. Additionally, boundary element method (BEM) and Voronoi diagram are used to generate training data. We verified the proposed method in terms of accuracy and time. The impedance can be predicted nearly 4 times faster than ground truth which calculated by BEM with a low error.

In this paper, a fast SerDes equalizer effect-included worst eye diagram estimation method is proposed for high-speed serial links. The proposed approach analytically integrates the effects of linear and nonlinear equalizers in the frequency and time domains, respectively, based on the behavior of the equalizers. This approach enables fast single-bit response (SBR) calculations without requiring input/output buffer information specifications, i.e., an algorithmic model interface (IBIS-AMI) model-based transient simulation. Additionally, a modified peak distortion analysis (PDA)-based worst eye estimation method was employed, including the outer contours. To validate the proposed method, tests were conducted in a peripheral component interconnect express (PCIe) Gen 6.0 channel environment configured with various equalizer combinations and different loss conditions. The proposed method achieves eye contour results comparable to those in conventional circuit simulations, operating up to 255 times faster than bit-by-bit methods and up to 66 times faster than statistical methods. The proposed method offers significant advantages in environments that require rapid exploration of optimal channel and equalizer combinations, providing substantial time savings and efficient evaluations.

In this paper, a deep reinforcement learning (DRL) approach that optimizes the power/ground ball map design within the ball grid array (BGA) package of 3D-ICs considering multiple-power-domain (MPD) environments is proposed. With the adoption of MPD in 3D-ICs, the BGA in the package substrate, which routes the power and ground to the appropriate power domain and components from the board, faces design challenges such as highly complex power noise between the domains and allocations considering multiple power densities. To address this design complexity, a U-net-based DRL method is adopted, which trains an optimal policy to obtain an optimal power/ground ball map to mitigate simultaneous switching noise (SSN). The U-net enables the conservation of semantic and spatial information simultaneously, allowing the proposed method to optimize the complex ball map effectively within the BGA package for MPD. Furthermore, the proposed method shows reusability and scalability by training with variously displaced current source center (CSC) balls and various ball map sizes while maintaining the power grouping design. The optimality performance of the proposed method is verified by comparing it to conventional optimization algorithms such as random search (RS) and a genetic algorithm (GA). The proposed method outperforms RS and GA in terms of the execution time and optimality performance across various tests with different ball map sizes and CSC positions.