In this paper, we propose and analyze a through silicon via (TSV) with a silicon dioxide well (SDW) to reduce leakage current in the design of a high-speed signaling and low-power consumption high-bandwidth memory (HBM) interface. In the proposed TSV, the SDW is inserted into the silicon substrate area between TSVs. By inserting the SDW, the silicon substrate’s effective conductivity and permittivity are lowered compared to a conventional TSV. The proposed TSV with the SDW improves insertion loss by up to 0.079 dB at 4 GHz by minimizing the leakage current. In addition, by reducing the effective permittivity of the silicon substrate, the difference in ratio between the capacitive coupling and inductive coupling is minimized. It is also possible to obtain a reduction in far-end crosstalk (FEXT) in the range of HBM interface signaling. RLGC modeling of the proposed TSV with the SDW is presented, and is physically analyzed based on the frequency-dependent equivalent capacitance and conductance of the silicon substrate. The proposed TSV with SDW is finally evaluated using an eye diagram, and the eye height and width improved by up to 13.7 % and 4.7 % at 8 Gb/s, respectively, compared to the conventional TSV. The proposed TSV also reduced dynamic power consumption by 48.1 % at 8 Gb/s, verifying the low-power structure.

In this paper, we propose, analyze and design a through silicon via (TSV) with a passive equalizer (PEQ) to mitigate the inter-symbol interference (ISI) and separate the return path for next-generation high bandwidth memory (HBM). The proposed HBM TSV includes a PEQ into the region between the signal TSV and ground TSV. We suggest the two-design structure of PEQ using the inductance and resistance. The proposed HBM TSV with PEQ provides two advantages. First, ISI can be suppressed by increasing the bandwidth or reducing the reflection caused by multi-drop topology. Second, the crosstalk can be reduced by separating return paths between the different signal TSVs. Based on the analytical modeling, the physical meaning of the proposed HBM TSV is presented. The channel loss, group delay, crosstalk, and time domain waveform are analyzed in terms of signal integrity for the proposed HBM TSV. Analysis and design method of the proposed HBM TSV are suggested to find an optimization point to define the resistance, inductance, and position of the PEQ. The proposed HBM TSV is evaluated based on the eye-diagram. Finally, from the practical point of view, the proposed HBM TSV fabrication process is also described.

It is necessary to reduce the crosstalk noise in high-speed signaling channels. In the channel routing area, the tabbed routing pattern is used to mitigate far-end crosstalk (FEXT), and the electrical length is controlled with a time domain reflectometer (TDR) and time domain transmission (TDT). However, unlike traditional channels having uniform width and space, the width and space of tabbed routing changes by segment, and the capacitance and inductance values of tabbed routing also change. In this paper, we propose a tabbed routing equivalent circuit modeling method using the segmentation approach. The proposed model was verified using 3D EM simulation and measurement results in the frequency domain. Based on the calculated inductance and capacitance parameters, we analyzed the insertion loss, FEXT, and self-impedance in the frequency domain, and TDT and FEXT in the time domain, by comparing the values of these metrics with and without tabbed routing. Using the proposed tabbed routing model, we analyzed tabbed routing with variations of design parameters based on self- and mutual-capacitance and inductance.

In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.

This article analyzes the characteristics of the harmonic components in wireless power transfer (WPT) systems depending on load in the LCC -S topology. In a WPT system, the equivalent load can be changed depending on the charging state. Depending on the equivalent load, the operation of the rectifier can be divided into two modes. The first is continuous conduction mode (CCM), and the second is discontinuous conduction mode (DCM). The harmonic characteristics in CCM and DCM operation were each analyzed. The electromagnetic field (EMF) level is the largest when the output power was the largest. However, the electromagnetic interference (EMI) level is largest when the magnitude of the load was at the boundary between CCM and DCM. In practical WPT systems, a dc–dc converter is used for output voltage regulation, and by using the converter, the equivalent load can be changeable. A design method to suppress the leakage magnetic field is proposed in terms of EMF and EMI. Through simulation and experiment, we verified when EMF and EMI levels have the largest value. Also, the effect of suppressing the leakage magnetic field was verified by changing the value of the equivalent load.

In this paper, we propose a 3D-IC PDN impedance prediction method using deep learning (DL). Unlike conventional application process (AP) and printed circuit board (PCB) design, our method proposes an effective solution to the problem of PDN design of 3D-IC, which requires accurate and fast impedance evaluation. For prediction, we construct regression neural network model based on VGG-16 with additional layers. Additionally, boundary element method (BEM) and Voronoi diagram are used to generate training data. We verified the proposed method in terms of accuracy and time. The impedance can be predicted nearly 4 times faster than ground truth which calculated by BEM with a low error.