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Prof. Eva Vidal
Universitat Politècnica de Catalunya

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0 Education for Sustainability
0 ICT4D
0 sustainability assessment
0 sustainability corporate responsibility social sciences business and management
0 sustainability competencies

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Journal article
Published: 17 July 2020 in Sustainability
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It is vital that subjects such as the circular economy, sustainable design, green computing or environmental engineering be included in the engineering curriculum. Education for sustainable development will enable engineers to develop sustainable products and provide sustainable services, thereby leading to a beneficial result for society and making an indispensable contribution to the Sustainable Development Goals achievement. As the last stage for students in academia, Degree Theses (Bachelor’s and Master’s) provide a good tool for reviewing the sustainability competencies developed during the degree, as well as being an opportunity for applying these competencies in a holistic way. In their Degree Theses, students should be able to demonstrate that they are aware of the need to introduce and assess sustainability in their future engineering projects. This paper presents a guide aimed at helping engineering students to design and develop sustainable projects, and analyzes the first results of its use in two schools of the Universitat Politècnica de Catalunya—BarcelonaTech. The proposal is based on a tool referred to as “the Sustainability Matrix”, in which cells contain questions that engineering students should take into account when undertaking their Degree Theses. The questions are related to the project development, the project exploitation and the possible risks involved, three aspects in accordance with the sustainability dimensions (economic, environmental and social). The Sustainability Matrix helps students to develop sustainable projects when they graduate, and teachers to assess how sustainability is incorporated across the curriculum in the subjects they teach and in the students’ Degree Theses.

ACS Style

Fermín Sánchez-Carracedo; David López; Carme Martín; Eva Vidal; Jose Cabré; Joan Climent. The Sustainability Matrix: A Tool for Integrating and Assessing Sustainability in the Bachelor and Master Theses of Engineering Degrees. Sustainability 2020, 12, 5755 .

AMA Style

Fermín Sánchez-Carracedo, David López, Carme Martín, Eva Vidal, Jose Cabré, Joan Climent. The Sustainability Matrix: A Tool for Integrating and Assessing Sustainability in the Bachelor and Master Theses of Engineering Degrees. Sustainability. 2020; 12 (14):5755.

Chicago/Turabian Style

Fermín Sánchez-Carracedo; David López; Carme Martín; Eva Vidal; Jose Cabré; Joan Climent. 2020. "The Sustainability Matrix: A Tool for Integrating and Assessing Sustainability in the Bachelor and Master Theses of Engineering Degrees." Sustainability 12, no. 14: 5755.

Conference paper
Published: 01 October 2019 in 2019 IEEE Frontiers in Education Conference (FIE)
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This Research to Practice Work in Progress paper presents the work conducted on the use of the Sustainability Map of Bachelor Engineering Degrees (a tool developed by the EDINSOST project) to analyze how Sustainable Development Goals (SDGs) are developed in each Degree. Over recent years, there has been a growth in the importance of working sustainability based on the SDGs. To identify which learning objective of each SDG corresponds to each learning outcome of the EDINSOST Sustainability Map, a correspondence matrix has been defined. The matrix contains the learning outcomes of the EDINSOST Sustainability Map in its rows, and the 17 SDGs in the columns. The cells of the matrix contain the learning objectives of the SDGs that correspond to each learning outcome of the EDINSOST Sustainability Map. This work in progress presents the first results of the process of mapping the SDGs into the EDINSOST Sustainability Map of Engineering Bachelor Degrees. Early results show that some of the 169 learning objectives are not applicable to Engineering Degrees. Likewise, we have seen that learning objectives have been defined more for policy makers than for engineers, and therefore adaptation is not an easy task. However, the work done has helped us to verify that the EDINSOST Sustainability Map can help in the introduction of the SDGs into the curriculum.

ACS Style

Fermin Sanchez; David Lopez; Ramon Bragos; Jose Cabre; Joan Climent; Eva Vidal; Carme Martin. Mapping the Sustainable Development Goals into the EDINSOST Sustainability Map of Bachelor Engineering Degrees. 2019 IEEE Frontiers in Education Conference (FIE) 2019, 1 -5.

AMA Style

Fermin Sanchez, David Lopez, Ramon Bragos, Jose Cabre, Joan Climent, Eva Vidal, Carme Martin. Mapping the Sustainable Development Goals into the EDINSOST Sustainability Map of Bachelor Engineering Degrees. 2019 IEEE Frontiers in Education Conference (FIE). 2019; ():1-5.

Chicago/Turabian Style

Fermin Sanchez; David Lopez; Ramon Bragos; Jose Cabre; Joan Climent; Eva Vidal; Carme Martin. 2019. "Mapping the Sustainable Development Goals into the EDINSOST Sustainability Map of Bachelor Engineering Degrees." 2019 IEEE Frontiers in Education Conference (FIE) , no. : 1-5.

Journal article
Published: 28 December 2018 in REDU. Revista de Docencia Universitaria
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La elaboración del informe de sostenibilidad de un proyecto de ingeniería es ya una práctica habitual en todas las empresas importantes del sector TIC. Los ingenieros que formamos ahora en las universidades deberán, sin duda, incluir informes de sostenibilidad en sus proyectos cuando ejerzan profesionalmente. La enseñanza necesaria para elaborar un buen informe de sostenibilidad de un Trabajo de Fin de Grado ya no es una opción, es una necesidad si queremos formar ingenieros de calidad. Desgraciadamente, no todos los profesores han tenido la experiencia necesaria para poder orientar a los estudiantes en la elaboración de un informe de sostenibilidad de un proyecto. Esto provoca que, a menudo, los estudiantes se encuentren perdidos al elaborar dicho informe, y acaben realizándolo sin hacer ninguna reflexión profunda sobre la sostenibilidad de su proyecto. Con el fin de orientar al estudiante en la valoración de la sostenibilidad de su Trabajo de Fin de Grado, en la Facultat de Informática de Barcelona, se ha diseñado una guía para la elaboración del informe de sostenibilidad de un Trabajo de Fin de Grado. En este artículo se presenta con detalle esta herramienta. La guía para elaborar el informe de sostenibilidad no sólo es de utilidad para los estudiantes, sino que también es una referencia para los directores y miembros de tribunal de los Trabajos de Fin de Grado.

ACS Style

J. Climent; J. Cabré; F. Sánchez; C. Martín; E. Vidal; D. López. El informe de sostenibilidad del Trabajo de Fin de Grado del área de las ingenierías. REDU. Revista de Docencia Universitaria 2018, 16, 75 -86.

AMA Style

J. Climent, J. Cabré, F. Sánchez, C. Martín, E. Vidal, D. López. El informe de sostenibilidad del Trabajo de Fin de Grado del área de las ingenierías. REDU. Revista de Docencia Universitaria. 2018; 16 (2):75-86.

Chicago/Turabian Style

J. Climent; J. Cabré; F. Sánchez; C. Martín; E. Vidal; D. López. 2018. "El informe de sostenibilidad del Trabajo de Fin de Grado del área de las ingenierías." REDU. Revista de Docencia Universitaria 16, no. 2: 75-86.

Journal article
Published: 01 August 2017 in Sensors and Actuators A: Physical
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ACS Style

Eva Vidal; Sergio Ruiz; Jérémy Duquenoy; J.L. González; Josep Altet. Differential temperature sensor with high sensitivity, wide dynamic range and digital offset calibration. Sensors and Actuators A: Physical 2017, 263, 373 -379.

AMA Style

Eva Vidal, Sergio Ruiz, Jérémy Duquenoy, J.L. González, Josep Altet. Differential temperature sensor with high sensitivity, wide dynamic range and digital offset calibration. Sensors and Actuators A: Physical. 2017; 263 ():373-379.

Chicago/Turabian Style

Eva Vidal; Sergio Ruiz; Jérémy Duquenoy; J.L. González; Josep Altet. 2017. "Differential temperature sensor with high sensitivity, wide dynamic range and digital offset calibration." Sensors and Actuators A: Physical 263, no. : 373-379.

Conference paper
Published: 01 December 2016 in 2016 IEEE Frontiers in Education Conference (FIE)
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This paper presents a tool developed to help engineers to design and develop sustainable projects. The tool has been designed to introduce and evaluate the sustainability of engineering projects in general, but here we show its application to assess the final project of an engineering degree. This tool is a guide for students to introduce and estimate the sustainability of their projects, but it also helps teachers to assess them. The tool is based on the Socratic Methodology and consists of a matrix where each cell contains several questions that students must consider during the project development and which they must answer in their project report. A positive or negative mark is assigned to every cell, and the sum of all marks states the project sustainability. However, the result is not as simplistic as a final number, but a descriptive sustainability analysis where questions are answered and every mark justified. A pilot test with some students has obtained good results, but the first Final Degree Project using this methodology will be read in July 2016.

ACS Style

Fermin Sanchez-Carracedo; Jose Cabre; Marc Alier; Eva Vidal; David Lopez; Carme Martin; Jordi Garcia. A learning tool to develop sustainable projects. 2016 IEEE Frontiers in Education Conference (FIE) 2016, 1 -9.

AMA Style

Fermin Sanchez-Carracedo, Jose Cabre, Marc Alier, Eva Vidal, David Lopez, Carme Martin, Jordi Garcia. A learning tool to develop sustainable projects. 2016 IEEE Frontiers in Education Conference (FIE). 2016; ():1-9.

Chicago/Turabian Style

Fermin Sanchez-Carracedo; Jose Cabre; Marc Alier; Eva Vidal; David Lopez; Carme Martin; Jordi Garcia. 2016. "A learning tool to develop sustainable projects." 2016 IEEE Frontiers in Education Conference (FIE) , no. : 1-9.

Journal article
Published: 06 October 2015 in IEEE Microwave and Wireless Components Letters
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This letter shows how a temperature sensor and a simple dc voltage multimeter can be used as instruments to determine the central frequency and 3 dB bandwidth of a 60 GHz linear power amplifier (PA). Compared to previous works, the dc temperature monitoring now proposed requires a much simpler and convenient measurement set-up. In this example, the temperature sensor is embedded in the same silicon die as the PA. Being placed in empty layout spaces next to it, it is proposed as a built-in test circuit.

ACS Style

Xavier Aragones; D. Mateo; J. L. Gonzalez; Eva Vidal; D. Gomez; B. Martineau; J. Altet. DC Temperature Measurements to Characterize the Central Frequency and 3 dB Bandwidth in mmW Power Amplifiers. IEEE Microwave and Wireless Components Letters 2015, 25, 745 -747.

AMA Style

Xavier Aragones, D. Mateo, J. L. Gonzalez, Eva Vidal, D. Gomez, B. Martineau, J. Altet. DC Temperature Measurements to Characterize the Central Frequency and 3 dB Bandwidth in mmW Power Amplifiers. IEEE Microwave and Wireless Components Letters. 2015; 25 (11):745-747.

Chicago/Turabian Style

Xavier Aragones; D. Mateo; J. L. Gonzalez; Eva Vidal; D. Gomez; B. Martineau; J. Altet. 2015. "DC Temperature Measurements to Characterize the Central Frequency and 3 dB Bandwidth in mmW Power Amplifiers." IEEE Microwave and Wireless Components Letters 25, no. 11: 745-747.

Conference paper
Published: 01 November 2011 in IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society
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The fault diagnosis field is in a continuous movement towards the generation of more reliable and powerful machine health monitoring schemes. Improved data processing methodologies are required to reach high diagnosis demands. For that reason, a contribution in motor fault classification methodology is presented. Different physical magnitudes such as phase currents, voltages and vibrations, are acquired from an electromechanical system based on Brushless DC motor. Statistical features, from time and frequency domains, are calculated to supply a classification algorithm based on Neural Network and enhanced by Genetic Algorithm. The significance of feature space dimensionality, related with the number of used features, for classification success is analyzed. The combination of a feature selection technique (by Sequential Floating Forward Selection), with a feature extraction technique (by Principal Component Analysis), is proposed as a novel hybrid feature reduction methodology to improve the classification performance in electrical machine fault diagnosis. The proposed methodology is validated experimentally and compared with classical feature reduction strategies.

ACS Style

M. Delgado; J. C. Urresty; L. Albiol; J. A. Ortega; A. García; L. Romeral; Eva Vidal. Motor fault classification system including a novel hybrid feature reduction methodology. IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society 2011, 2388 -2393.

AMA Style

M. Delgado, J. C. Urresty, L. Albiol, J. A. Ortega, A. García, L. Romeral, Eva Vidal. Motor fault classification system including a novel hybrid feature reduction methodology. IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society. 2011; ():2388-2393.

Chicago/Turabian Style

M. Delgado; J. C. Urresty; L. Albiol; J. A. Ortega; A. García; L. Romeral; Eva Vidal. 2011. "Motor fault classification system including a novel hybrid feature reduction methodology." IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society , no. : 2388-2393.

Conference paper
Published: 01 May 2010 in Proceedings of 2010 IEEE International Symposium on Circuits and Systems
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This paper deals with the proposal of a new topology for a gm-C continuous time filter which allows the adjustment and tuning of its characteristic parameters (ωO and Q) in an independent way (without cross-tuning), thereby extending the Q range of the filter for a particular ωO value. Additionally a comparison of three different Q-tuning algorithms is presented. It is shown that an LMS-based Q-control strategy allows to overcome the intrinsic dependence between the Q and ωO tuning loops. The combination of both the proposed filter topology and the selected control loop algorithms results in an enhanced transient performance as well as an improvement in terms of cross-detuning.Postprint (published version

ACS Style

Herminio Martinez; Eva Vidal; Andrea Canto; Alberto Poveda; Francesc Guinjoan. Bandwidth-enhancement gm-C filter with independent ωO and Q tuning mechanisms in both topology and control loops. Proceedings of 2010 IEEE International Symposium on Circuits and Systems 2010, 1 .

AMA Style

Herminio Martinez, Eva Vidal, Andrea Canto, Alberto Poveda, Francesc Guinjoan. Bandwidth-enhancement gm-C filter with independent ωO and Q tuning mechanisms in both topology and control loops. Proceedings of 2010 IEEE International Symposium on Circuits and Systems. 2010; ():1.

Chicago/Turabian Style

Herminio Martinez; Eva Vidal; Andrea Canto; Alberto Poveda; Francesc Guinjoan. 2010. "Bandwidth-enhancement gm-C filter with independent ωO and Q tuning mechanisms in both topology and control loops." Proceedings of 2010 IEEE International Symposium on Circuits and Systems , no. : 1.

Journal article
Published: 31 October 2009 in AEU - International Journal of Electronics and Communications
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Four cross-coupled MOS transistors operating as switches implement a very compact, fast, low-power and precise minimum and maximum current selector. Local positive feedback allows the circuit to work without the need of any control inputs and ensures very high sensitivity. Experimental results confirm the simulations and the analyzed second-order effects. Applications include min–max current selection and precision differential rectification. An application example of the cell to build a similarity circuit is reported.

ACS Style

Jordi Madrenas; Daniel Fernández; Jordi Cosp-Vilella; Luis Arturo Martinez-Alvarado; Eduard Alarcón; Eva Vidal; Gerard Villar. Self-controlled 4-transistor low-power min–max current selector. AEU - International Journal of Electronics and Communications 2009, 63, 871 -876.

AMA Style

Jordi Madrenas, Daniel Fernández, Jordi Cosp-Vilella, Luis Arturo Martinez-Alvarado, Eduard Alarcón, Eva Vidal, Gerard Villar. Self-controlled 4-transistor low-power min–max current selector. AEU - International Journal of Electronics and Communications. 2009; 63 (10):871-876.

Chicago/Turabian Style

Jordi Madrenas; Daniel Fernández; Jordi Cosp-Vilella; Luis Arturo Martinez-Alvarado; Eduard Alarcón; Eva Vidal; Gerard Villar. 2009. "Self-controlled 4-transistor low-power min–max current selector." AEU - International Journal of Electronics and Communications 63, no. 10: 871-876.

Journal article
Published: 04 June 2009 in Analog Integrated Circuits and Signal Processing
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Continuous-time filters with automatic tuning loops are nonlinear feedback systems that are potentially unstable. To ensure stability, particularly if the design of the loop controllers is to be improved, the appropriate linear dynamic modeling of the tunable filter, including control inputs, should be attained. This work aims to present a general dynamic modeling of continuous-time analog filters with automatic tuning capability. The general analysis leads to an equivalent small-signal linearized incremental model, from which transfer functions between output variables and control voltages are obtained. Subsequent to the analysis, it is possible to design compensated loops with enhanced stability and dynamic performance. By way of example, the modeling of a particular band-pass CMOS continuous-time analog filter is presented in this paper. Two transfer functions are derived: the transfer function between the output phase shift and the central frequency control voltage, and that between the output amplitude and the quality factor control voltage. These functions are required to properly tune the central frequency and quality factor parameters. This modeling makes it possible to propose an adaptive controller with improved stability and a possible implementation for such a controller. Finally, experimental results are shown for a CMOS 0.8 μm technology.

ACS Style

Herminio Martínez; Eva Vidal; Eduard Alarcón; Alberto Poveda. Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops. Analog Integrated Circuits and Signal Processing 2009, 61, 231 -246.

AMA Style

Herminio Martínez, Eva Vidal, Eduard Alarcón, Alberto Poveda. Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops. Analog Integrated Circuits and Signal Processing. 2009; 61 (3):231-246.

Chicago/Turabian Style

Herminio Martínez; Eva Vidal; Eduard Alarcón; Alberto Poveda. 2009. "Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops." Analog Integrated Circuits and Signal Processing 61, no. 3: 231-246.

Proceedings article
Published: 22 September 2006 in 2006 IEEE International Symposium on Circuits and Systems
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Continuous-time filters (CTF) with automatic tuning loops are nonlinear feedback systems with potential instability. Therefore, the appropriate linear dynamic modeling of the tunable filter should be obtained to assure stability in case an improved design of the loop controllers is to be carried out. With this aim, starting from a general and systematic analysis in order to obtain an equivalent small-signal linearised incremental model, from which transfer functions between output variables and control voltages are derived, the subsequent design of compensated loops with enhanced stability and dynamic performance is proposed. In particular, this modeling allows proposing both a non-adaptive and adaptive controllers with improved stability, together with their implementation. As a demonstrative example of application, the modeling of a particular band-pass CMOS CTF is presented in this paper. Experimental results are shown for a CMOS 0.8-mum technology

ACS Style

H. Martinez; Eva Vidal; E. Alarcon; A. Poveda. Improving the Stability of On-Chip Automatic Tuning Loops for Continuous-Time Filters with an Analog Adaptive Controller. 2006 IEEE International Symposium on Circuits and Systems 2006, 1 .

AMA Style

H. Martinez, Eva Vidal, E. Alarcon, A. Poveda. Improving the Stability of On-Chip Automatic Tuning Loops for Continuous-Time Filters with an Analog Adaptive Controller. 2006 IEEE International Symposium on Circuits and Systems. 2006; ():1.

Chicago/Turabian Style

H. Martinez; Eva Vidal; E. Alarcon; A. Poveda. 2006. "Improving the Stability of On-Chip Automatic Tuning Loops for Continuous-Time Filters with an Analog Adaptive Controller." 2006 IEEE International Symposium on Circuits and Systems , no. : 1.

Conference paper
Published: 27 July 2005 in 2005 IEEE International Symposium on Circuits and Systems
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The design and implementation of a CMOS analog integrated circuit that provides multi-mode control laws for high-frequency switching power converters is described. The general-purpose controller circuit is capable of implementing classical PWM control, current-mode control with compensating ramp, sliding-mode control and one-cycle control. The main building block within the controller architecture is the current conveyor. Additionally, the IC includes power MOSFETs and their drivers. Layout details for a CMOS 0.35 /spl mu/m technology implementation are discussed.

ACS Style

E. Alarcon; G. Villar; H. Martinez; Eva Vidal; S. Porta; F. Guinjoan; A. Poveda. Multi-Mode Controller CMOS Integrated Circuit for Switching Power Converters. 2005 IEEE International Symposium on Circuits and Systems 2005, 4457 .

AMA Style

E. Alarcon, G. Villar, H. Martinez, Eva Vidal, S. Porta, F. Guinjoan, A. Poveda. Multi-Mode Controller CMOS Integrated Circuit for Switching Power Converters. 2005 IEEE International Symposium on Circuits and Systems. 2005; ():4457.

Chicago/Turabian Style

E. Alarcon; G. Villar; H. Martinez; Eva Vidal; S. Porta; F. Guinjoan; A. Poveda. 2005. "Multi-Mode Controller CMOS Integrated Circuit for Switching Power Converters." 2005 IEEE International Symposium on Circuits and Systems , no. : 4457.

Proceedings article
Published: 27 July 2005 in 2005 IEEE International Symposium on Circuits and Systems
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In this work, we propose a mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation circuits using a modified LEGION algorithm. As a result of the combination of excitatory synapses (to synchronize coupled oscillators) and global inhibition (to separate unconnected objects) the oscillator array can segment the image objects by phase-encoding. However, the synchronizing mechanism is sensitive to frequency dispersion, and hence a mismatch-tolerant oscillator architecture is a key point for correct operation. With a feedback scheme based on switched capacitors and a large time constant low-pass filter, frequency variations are significantly reduced. The excitatory synapse circuit enables oscillator synchronization and is implemented by a quasi floating-gate MOS transistor. Transistor-level simulation results for CMOS 0.35 /spl mu/m technology are presented to validate the functionality of the mismatch-tolerant oscillator and synapse.

ACS Style

D. Fernández; G. Villar; Eva Vidal; E. Alarcon; J. Cosp; J. Madrenas. Mismatch-Tolerant CMOS Oscillator and Excitatory Synapse for Bioinspired Image Segmentation. 2005 IEEE International Symposium on Circuits and Systems 2005, 1 .

AMA Style

D. Fernández, G. Villar, Eva Vidal, E. Alarcon, J. Cosp, J. Madrenas. Mismatch-Tolerant CMOS Oscillator and Excitatory Synapse for Bioinspired Image Segmentation. 2005 IEEE International Symposium on Circuits and Systems. 2005; ():1.

Chicago/Turabian Style

D. Fernández; G. Villar; Eva Vidal; E. Alarcon; J. Cosp; J. Madrenas. 2005. "Mismatch-Tolerant CMOS Oscillator and Excitatory Synapse for Bioinspired Image Segmentation." 2005 IEEE International Symposium on Circuits and Systems , no. : 1.

Conference paper
Published: 27 July 2005 in 2005 IEEE International Symposium on Circuits and Systems
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ACS Style

J. Madrenas; D. Fernandez; Jordi Cosp-Vilella; E. Alarcon; E. Vidal; G. Villar. Selective Similarity Function for VLSI Analog Signal Processing. 2005 IEEE International Symposium on Circuits and Systems 2005, 1 .

AMA Style

J. Madrenas, D. Fernandez, Jordi Cosp-Vilella, E. Alarcon, E. Vidal, G. Villar. Selective Similarity Function for VLSI Analog Signal Processing. 2005 IEEE International Symposium on Circuits and Systems. 2005; ():1.

Chicago/Turabian Style

J. Madrenas; D. Fernandez; Jordi Cosp-Vilella; E. Alarcon; E. Vidal; G. Villar. 2005. "Selective Similarity Function for VLSI Analog Signal Processing." 2005 IEEE International Symposium on Circuits and Systems , no. : 1.

Journal article
Published: 01 January 2005 in Analog Integrated Circuits and Signal Processing
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This letter describes the design and implementation of a synchronizable compact CMOS oscillator. By using a fully differential topology, a reduction in area occupancy together with an improved robustness in front of on-chip interferences is achieved. Post-layout simulation results and experimental results for a standard CMOS 0.35 驴 m technology are presented to validate the functionality of the tunable oscillator.

ACS Style

G. Villar; E. Alarcón; Eva Vidal; J. Cosp; J. Madrenas; Jordi Cosp-Vilella. Synchronizable Compact CMOS Oscillator. Analog Integrated Circuits and Signal Processing 2005, 42, 179 -183.

AMA Style

G. Villar, E. Alarcón, Eva Vidal, J. Cosp, J. Madrenas, Jordi Cosp-Vilella. Synchronizable Compact CMOS Oscillator. Analog Integrated Circuits and Signal Processing. 2005; 42 (2):179-183.

Chicago/Turabian Style

G. Villar; E. Alarcón; Eva Vidal; J. Cosp; J. Madrenas; Jordi Cosp-Vilella. 2005. "Synchronizable Compact CMOS Oscillator." Analog Integrated Circuits and Signal Processing 42, no. 2: 179-183.

Proceedings article
Published: 20 September 2004 in 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
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Continuous-time filters with automatic tuning loops are feedback nonlinear systems with potential instability. If a stability study is to be carried out, even if it is at least local, the appropriate linear dynamical modelling of the filter should be obtained. This modelling is mandatory if an improved design of the loop controllers is to be carried out. This work presents the dynamic modelling of a CMOS continuous-time analog filter with automatic tuning capability. The analysis leads to an equivalent small-signal linearised incremental model from which transfer functions between output variables and control voltages are obtained. The dynamic modelling of both the phase-shift between input and output signals as well as the output amplitude, required to properly tune both frequency and quality factor parameters, is presented. The analysis leads to the design of a compensated loop with enhanced stability and dynamic performance.

ACS Style

H. Martinez; Eva Vidal; E. Alarcon; A. Poveda. Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops. 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) 2004, 1 .

AMA Style

H. Martinez, Eva Vidal, E. Alarcon, A. Poveda. Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops. 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512). 2004; ():1.

Chicago/Turabian Style

H. Martinez; Eva Vidal; E. Alarcon; A. Poveda. 2004. "Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops." 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) , no. : 1.

Journal article
Published: 01 February 2004 in Analog Integrated Circuits and Signal Processing
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ACS Style

Eva Vidal; Eduard Alarcón; Barrie Gilbert. Guest Editorial. Analog Integrated Circuits and Signal Processing 2004, 38, 79 -82.

AMA Style

Eva Vidal, Eduard Alarcón, Barrie Gilbert. Guest Editorial. Analog Integrated Circuits and Signal Processing. 2004; 38 (3):79-82.

Chicago/Turabian Style

Eva Vidal; Eduard Alarcón; Barrie Gilbert. 2004. "Guest Editorial." Analog Integrated Circuits and Signal Processing 38, no. 3: 79-82.

Journal article
Published: 01 February 2004 in Analog Integrated Circuits and Signal Processing
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ACS Style

Eva Vidal; Eduard Alarcón; Barrie Gilbert. Up-to-Date Bibliography of Current-Mode Design. Analog Integrated Circuits and Signal Processing 2004, 38, 245 -262.

AMA Style

Eva Vidal, Eduard Alarcón, Barrie Gilbert. Up-to-Date Bibliography of Current-Mode Design. Analog Integrated Circuits and Signal Processing. 2004; 38 (2/3):245-262.

Chicago/Turabian Style

Eva Vidal; Eduard Alarcón; Barrie Gilbert. 2004. "Up-to-Date Bibliography of Current-Mode Design." Analog Integrated Circuits and Signal Processing 38, no. 2/3: 245-262.

Conference paper
Published: 25 June 2003 in 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628)
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ACS Style

A. Ravindran; E. Vidal; M. Ismail. A digitally generated exponential function for dB-linear CMOS variable gain amplifiers. 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628) 2003, 1 .

AMA Style

A. Ravindran, E. Vidal, M. Ismail. A digitally generated exponential function for dB-linear CMOS variable gain amplifiers. 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628). 2003; ():1.

Chicago/Turabian Style

A. Ravindran; E. Vidal; M. Ismail. 2003. "A digitally generated exponential function for dB-linear CMOS variable gain amplifiers." 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628) , no. : 1.

Conference paper
Published: 25 June 2003 in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
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This paper describes the study, synthesis and analog microelectronic implementation of a method for obtaining the instantaneous average value of a signal, in the context of switching power converter control. A functional description as well as analytical conditions describing the validity of the method are included. At circuit level, the adopted current-mode design approach results in low circuit complexity and high dynamic performance. Simulation results for a microelectronic realization in CMOS 0.35 /spl mu/m show proper behavior up to 1 MHz switching frequency.

ACS Style

G. Villar; E. Alarcon; H. Martinez; D. Biel; Eva Vidal; A. Poveda. Averaging circuit for switching power converter control: a CMOS current-mode integrated implementation. 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) 2003, 1 .

AMA Style

G. Villar, E. Alarcon, H. Martinez, D. Biel, Eva Vidal, A. Poveda. Averaging circuit for switching power converter control: a CMOS current-mode integrated implementation. 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353). 2003; ():1.

Chicago/Turabian Style

G. Villar; E. Alarcon; H. Martinez; D. Biel; Eva Vidal; A. Poveda. 2003. "Averaging circuit for switching power converter control: a CMOS current-mode integrated implementation." 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) , no. : 1.