This paper presents a cascaded gate driver power supply configuration to reduce the common mode (CM) current in phase-shifted full-bridge (PSFB) converters. In such converters, there are at least two dV=dt sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (power supplies and control signal isolation units), which can increase the conducted electromagnetic interference (EMI) perturbations. This paper is focused on the analysis of a new gate driver power supply configuration, which reduces the CM currents that circulate in the control part of the switching cells. This improvement is achieved by modifying the impedance network of CM current pathways. Experimental results are provided to prove the effectiveness of the new gate driver power supply configuration on a PSFB converter based on SiC-MOSFETs devices.

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.

This paper presents a cascaded gate driver architecture to improve the switching speed of series-connected power devices. The main idea is to propose a new technique to increase the dV=dt of the devices when their voltages are already balanced. In complex power converters like multi-cell and multi-level topologies, and series-connected power devices, many driver circuits are required and implemented. In such converters, there are several dV=dt sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (supplies and control signal isolation units), which can amplify the conducted electromagnetic interference (EMI) perturbations and therefore the switching speed of the power devices can be affected. This paper is focused on the analysis of a new cascaded configuration of gate drivers to increase the switching speed, and consequently reducing the switching losses of the series-connected transistor topologies. This improvement is achieved by reducing the equivalent parasitic capacitance of the gate driver circuitry considering the gate driver architectures: a new concept of Cascaded Gate Driver is presented. Theoretical and experimental measurements are used to support the Cascade Gate Driver Architecture proposed in this paper.

Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations: Ce travail de thèse étudie de nouvelles configurations d'alimentation de commande rapprochée et un nouveau concept de packaging afin d'améliorer les performances des MOSFETs SiC connectés en série. Les nouvelles configurations de commande rapprochée sont proposées afin de réduire les courants de bruit qui circulent dans la partie commande du système électrique. De plus, une nouvelle alimentation de commande de grille est proposée pour augmenter le dv / dt de la cellule de commutation. Ces améliorations, c'est-à-dire la réduction du courant de bruit et l'amplification du dv/dt, sont obtenues en modifiant l'impédance des circuits de commande de grille. Le nouveau concept de packaging est proposé afin d'améliorer les performances d’équilibrage de tension. Les nouvelles configurations de commande rapprochée et les concepts de packaging sont introduits et analysés grâce à des modèles analytique et des simulations. Ensuite, des essayes expérimentales sont effectuées pour confirmer que les concepts proposés sont meilleurs que les concepts traditionnels en termes d'équilibrage de tension, de vitesse de commutation et de réduction EMI conduite.