A new 3-D power module dedicated to SiC mosfet is presented. It is based on printed circuit board embedded die technology and is compared with a standard power module. After considering the characteristics that contribute to optimal switching performances from the packaging point of view, both modules are characterized in terms of switching behavior and electromagnetic interference emissions. The results show better performances of the 3-D embedded die module with stray inductances below 2 nH and two times less common mode noise.

This article presents local shielding techniques applied to a half-bridge inverter leg with the aim to reduce the common-mode (CM) current noise at converter’s dc input. The research study is conducted for 650-V enhancement mode Gallium Nitride power transistor switches. Main contributors of parasitic capacitances referred to the inverter-leg middle point node are identified. Then, shielding solutions are proposed to reduce the CM current emission by these capacitances. Respecting the precautions concerning the isolation of CM currents of the half-bridge inverter leg, the electromagnetic compatibility measurement setup is developed. Experimental step-by-step addition of local shielding copper layers to different contributors of middle point capacitance shows progressive attenuation of CM noise spectra.

Sustainability in power electronics is a recent research topic. It takes place among current actions to grasp design choices that enable eco-design and circular economy in the domain. This paper shows the results and analysis of a literature review at the intersection of power electronics and sustainability without considering the reliability study of the power electronics systems. The first part explains the scope of the study. The second part shows a bibliometric analysis of the collected publications that underlines a pioneering position at the European level. The third part details the state-of-the-art and its analysis over four investigation topics which are: tools and methods, indicators, circularity and materials. This paper and the work behind are the results of collaboration at the French national level, as part of the workgroup CEPPS (Convertisseurs Electronique de Puissance Plus Soutenables—More Sustainable Power Electronics Converters) supported by the CNRS (Centre National de la Recherche Scientifique—French National Centre for Scientific Research) research group SEEDS (Systèmes d’énergie électrique dans leurs dimensions sociétales—Societal dimensions of electrical energy systems).

This paper presents a cascaded gate driver power supply configuration to reduce the common mode (CM) current in phase-shifted full-bridge (PSFB) converters. In such converters, there are at least two dV=dt sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (power supplies and control signal isolation units), which can increase the conducted electromagnetic interference (EMI) perturbations. This paper is focused on the analysis of a new gate driver power supply configuration, which reduces the CM currents that circulate in the control part of the switching cells. This improvement is achieved by modifying the impedance network of CM current pathways. Experimental results are provided to prove the effectiveness of the new gate driver power supply configuration on a PSFB converter based on SiC-MOSFETs devices.

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.

This paper presents a cascaded gate driver architecture to improve the switching speed of series-connected power devices. The main idea is to propose a new technique to increase the dV=dt of the devices when their voltages are already balanced. In complex power converters like multi-cell and multi-level topologies, and series-connected power devices, many driver circuits are required and implemented. In such converters, there are several dV=dt sources generated at different floating points associated to the parasitic capacitances of the isolated barriers of the gate drivers (supplies and control signal isolation units), which can amplify the conducted electromagnetic interference (EMI) perturbations and therefore the switching speed of the power devices can be affected. This paper is focused on the analysis of a new cascaded configuration of gate drivers to increase the switching speed, and consequently reducing the switching losses of the series-connected transistor topologies. This improvement is achieved by reducing the equivalent parasitic capacitance of the gate driver circuitry considering the gate driver architectures: a new concept of Cascaded Gate Driver is presented. Theoretical and experimental measurements are used to support the Cascade Gate Driver Architecture proposed in this paper.